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irqchip/sifive-plic: Fix maximum priority threshold value

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As per the PLIC specification, maximum priority threshold value is 0x7
not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
there may be some implementation which checks the upper bound resulting in
an illegal access.

Fixes: ccbe80bad5 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200403014609.71831-1-atish.patra@wdc.com
This commit is contained in:
Atish Patra 2020-04-02 18:46:09 -07:00 committed by Marc Zyngier
parent 3688b0db5c
commit d727be7bbf
1 changed files with 1 additions and 1 deletions
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2
drivers/irqchip/irq-sifive-plic.c
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@ -56,7 +56,7 @@
#define CONTEXT_THRESHOLD 0x00
#define CONTEXT_CLAIM 0x04
#define PLIC_DISABLE_THRESHOLD 0xf
#define PLIC_DISABLE_THRESHOLD 0x7
#define PLIC_ENABLE_THRESHOLD 0
struct plic_priv {