i.MX31ADS: Add CPLD interrupts demultiplexing (take 3).
Needed for 8250 serial port and CS89x0 ethernet interface. Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -22,6 +22,7 @@
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/serial_8250.h>
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#include <linux/irq.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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@ -106,6 +107,88 @@ static inline void mxc_init_imx_uart(void)
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}
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#endif /* !SERIAL_IMX */
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static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 imr_val;
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u32 int_valid;
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u32 expio_irq;
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imr_val = __raw_readw(PBC_INTMASK_SET_REG);
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int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
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expio_irq = MXC_EXP_IO_BASE;
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for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
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if ((int_valid & 1) == 0)
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continue;
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generic_handle_irq(expio_irq);
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}
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}
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/*
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* Disable an expio pin's interrupt by setting the bit in the imr.
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* @param irq an expio virtual irq number
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*/
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static void expio_mask_irq(u32 irq)
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{
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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/* mask the interrupt */
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__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
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__raw_readw(PBC_INTMASK_CLEAR_REG);
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}
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/*
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* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
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* @param irq an expanded io virtual irq number
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*/
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static void expio_ack_irq(u32 irq)
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{
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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/* clear the interrupt status */
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__raw_writew(1 << expio, PBC_INTSTATUS_REG);
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}
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/*
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* Enable a expio pin's interrupt by clearing the bit in the imr.
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* @param irq a expio virtual irq number
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*/
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static void expio_unmask_irq(u32 irq)
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{
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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/* unmask the interrupt */
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__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
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}
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static struct irq_chip expio_irq_chip = {
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.ack = expio_ack_irq,
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.mask = expio_mask_irq,
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.unmask = expio_unmask_irq,
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};
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static void __init mx31ads_init_expio(void)
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{
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int i;
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printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
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/*
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* Configure INT line as GPIO input
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*/
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mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO));
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/* disable the interrupt and clear the status */
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__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
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__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
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for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
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i++) {
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set_irq_chip(i, &expio_irq_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
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set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
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}
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/*!
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* This structure defines static mappings for the i.MX31ADS board.
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*/
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@ -142,6 +225,12 @@ void __init mx31ads_map_io(void)
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iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
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}
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void __init mx31ads_init_irq(void)
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{
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mxc_init_irq();
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mx31ads_init_expio();
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}
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/*!
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* Board specific initialization.
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*/
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@ -171,7 +260,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
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.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
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.boot_params = PHYS_OFFSET + 0x100,
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.map_io = mx31ads_map_io,
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.init_irq = mxc_init_irq,
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.init_irq = mx31ads_init_irq,
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.init_machine = mxc_board_init,
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.timer = &mx31ads_timer,
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MACHINE_END
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@ -90,6 +90,9 @@
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#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
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#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
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#define MXC_EXP_IO_BASE (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES)
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#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
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#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
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#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
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#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
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