drm/amd/display: Define registers for dcn10
Define register for dcn10 for future changes Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -260,6 +260,7 @@ struct dcn10_stream_enc_registers {
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
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SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
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SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
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SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
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@ -364,6 +365,7 @@ struct dcn10_stream_enc_registers {
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type DP_SEC_GSP5_ENABLE;\
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type DP_SEC_GSP6_ENABLE;\
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type DP_SEC_GSP7_ENABLE;\
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type DP_SEC_GSP7_SEND;\
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type DP_SEC_MPG_ENABLE;\
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type DP_VID_STREAM_DIS_DEFER;\
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type DP_VID_STREAM_ENABLE;\
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