drm/i915: Enable i915 perf stream for Haswell OA unit
Gen graphics hardware can be set up to periodically write snapshots of performance counters into a circular buffer via its Observation Architecture and this patch exposes that capability to userspace via the i915 perf interface. v2: Make sure to initialize ->specific_ctx_id when opening, without relying on _pin_notify hook, in case ctx already pinned. v3: Revert back to pinning ctx upfront when opening stream, removing need to hook in to pinning and to update OACONTROL on the fly. Signed-off-by: Robert Bragg <robert@sixbynine.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Sourab Gupta <sourab.gupta@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-7-robert@sixbynine.orghifive-unleashed-5.1
Robert Bragg
Daniel Vetter
parent
8a3003dd93
commit
d79651522e
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@ -1797,6 +1797,11 @@ struct intel_wm_config {
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bool sprites_scaled;
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};
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struct i915_oa_format {
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u32 format;
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int size;
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};
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struct i915_oa_reg {
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i915_reg_t addr;
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u32 value;
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@ -1817,11 +1822,6 @@ struct i915_perf_stream_ops {
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*/
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void (*disable)(struct i915_perf_stream *stream);
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/* Return: true if any i915 perf records are ready to read()
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* for this stream.
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*/
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bool (*can_read)(struct i915_perf_stream *stream);
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/* Call poll_wait, passing a wait queue that will be woken
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* once there is something ready to read() for the stream
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*/
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@ -1831,9 +1831,7 @@ struct i915_perf_stream_ops {
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/* For handling a blocking read, wait until there is something
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* to ready to read() for the stream. E.g. wait on the same
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* wait queue that would be passed to poll_wait() until
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* ->can_read() returns true (if its safe to call ->can_read()
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* without the i915 perf lock held).
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* wait queue that would be passed to poll_wait().
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*/
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int (*wait_unlocked)(struct i915_perf_stream *stream);
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@ -1873,11 +1871,28 @@ struct i915_perf_stream {
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struct list_head link;
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u32 sample_flags;
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int sample_size;
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struct i915_gem_context *ctx;
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bool enabled;
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struct i915_perf_stream_ops *ops;
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const struct i915_perf_stream_ops *ops;
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};
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struct i915_oa_ops {
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void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
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int (*enable_metric_set)(struct drm_i915_private *dev_priv);
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void (*disable_metric_set)(struct drm_i915_private *dev_priv);
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void (*oa_enable)(struct drm_i915_private *dev_priv);
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void (*oa_disable)(struct drm_i915_private *dev_priv);
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void (*update_oacontrol)(struct drm_i915_private *dev_priv);
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void (*update_hw_ctx_id_locked)(struct drm_i915_private *dev_priv,
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u32 ctx_id);
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int (*read)(struct i915_perf_stream *stream,
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char __user *buf,
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size_t count,
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size_t *offset);
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bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
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};
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struct drm_i915_private {
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@ -2177,16 +2192,47 @@ struct drm_i915_private {
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struct {
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bool initialized;
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struct mutex lock;
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struct list_head streams;
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spinlock_t hook_lock;
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struct {
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u32 metrics_set;
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struct i915_perf_stream *exclusive_stream;
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u32 specific_ctx_id;
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struct i915_vma *pinned_rcs_vma;
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struct hrtimer poll_check_timer;
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wait_queue_head_t poll_wq;
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bool pollin;
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bool periodic;
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int period_exponent;
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int timestamp_frequency;
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int tail_margin;
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int metrics_set;
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const struct i915_oa_reg *mux_regs;
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int mux_regs_len;
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const struct i915_oa_reg *b_counter_regs;
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int b_counter_regs_len;
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struct {
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struct i915_vma *vma;
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u8 *vaddr;
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int format;
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int format_size;
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} oa_buffer;
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u32 gen7_latched_oastatus1;
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struct i915_oa_ops ops;
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const struct i915_oa_format *oa_formats;
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int n_builtin_sets;
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} oa;
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} perf;
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File diff suppressed because it is too large
Load Diff
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@ -616,6 +616,343 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
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#define GEN7_OACONTROL _MMIO(0x2360)
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#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
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#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
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#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
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#define GEN7_OACONTROL_TIMER_ENABLE (1<<5)
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#define GEN7_OACONTROL_FORMAT_A13 (0<<2)
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#define GEN7_OACONTROL_FORMAT_A29 (1<<2)
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#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2<<2)
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#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3<<2)
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#define GEN7_OACONTROL_FORMAT_B4_C8 (4<<2)
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#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5<<2)
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#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6<<2)
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#define GEN7_OACONTROL_FORMAT_C4_B8 (7<<2)
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#define GEN7_OACONTROL_FORMAT_SHIFT 2
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#define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1)
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#define GEN7_OACONTROL_ENABLE (1<<0)
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#define GEN8_OACTXID _MMIO(0x2364)
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#define GEN8_OACONTROL _MMIO(0x2B00)
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#define GEN8_OA_REPORT_FORMAT_A12 (0<<2)
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#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2)
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#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5<<2)
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#define GEN8_OA_REPORT_FORMAT_C4_B8 (7<<2)
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#define GEN8_OA_REPORT_FORMAT_SHIFT 2
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#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1<<1)
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#define GEN8_OA_COUNTER_ENABLE (1<<0)
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#define GEN8_OACTXCONTROL _MMIO(0x2360)
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#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
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#define GEN8_OA_TIMER_PERIOD_SHIFT 2
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#define GEN8_OA_TIMER_ENABLE (1<<1)
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#define GEN8_OA_COUNTER_RESUME (1<<0)
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#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
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#define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3)
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#define GEN7_OABUFFER_EDGE_TRIGGER (1<<2)
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#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1)
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#define GEN7_OABUFFER_RESUME (1<<0)
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#define GEN8_OABUFFER _MMIO(0x2b14)
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#define GEN7_OASTATUS1 _MMIO(0x2364)
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#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
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#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1<<2)
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#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1<<1)
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#define GEN7_OASTATUS1_REPORT_LOST (1<<0)
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#define GEN7_OASTATUS2 _MMIO(0x2368)
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#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
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#define GEN8_OASTATUS _MMIO(0x2b08)
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#define GEN8_OASTATUS_OVERRUN_STATUS (1<<3)
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#define GEN8_OASTATUS_COUNTER_OVERFLOW (1<<2)
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#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1<<1)
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#define GEN8_OASTATUS_REPORT_LOST (1<<0)
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#define GEN8_OAHEADPTR _MMIO(0x2B0C)
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#define GEN8_OATAILPTR _MMIO(0x2B10)
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#define OABUFFER_SIZE_128K (0<<3)
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#define OABUFFER_SIZE_256K (1<<3)
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#define OABUFFER_SIZE_512K (2<<3)
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#define OABUFFER_SIZE_1M (3<<3)
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#define OABUFFER_SIZE_2M (4<<3)
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#define OABUFFER_SIZE_4M (5<<3)
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#define OABUFFER_SIZE_8M (6<<3)
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#define OABUFFER_SIZE_16M (7<<3)
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#define OA_MEM_SELECT_GGTT (1<<0)
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#define EU_PERF_CNTL0 _MMIO(0xe458)
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#define GDT_CHICKEN_BITS _MMIO(0x9840)
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#define GT_NOA_ENABLE 0x00000080
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/*
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* OA Boolean state
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*/
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#define OAREPORTTRIG1 _MMIO(0x2740)
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#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
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#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
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#define OAREPORTTRIG2 _MMIO(0x2744)
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#define OAREPORTTRIG2_INVERT_A_0 (1<<0)
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#define OAREPORTTRIG2_INVERT_A_1 (1<<1)
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#define OAREPORTTRIG2_INVERT_A_2 (1<<2)
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#define OAREPORTTRIG2_INVERT_A_3 (1<<3)
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#define OAREPORTTRIG2_INVERT_A_4 (1<<4)
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#define OAREPORTTRIG2_INVERT_A_5 (1<<5)
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#define OAREPORTTRIG2_INVERT_A_6 (1<<6)
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#define OAREPORTTRIG2_INVERT_A_7 (1<<7)
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#define OAREPORTTRIG2_INVERT_A_8 (1<<8)
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#define OAREPORTTRIG2_INVERT_A_9 (1<<9)
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#define OAREPORTTRIG2_INVERT_A_10 (1<<10)
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#define OAREPORTTRIG2_INVERT_A_11 (1<<11)
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#define OAREPORTTRIG2_INVERT_A_12 (1<<12)
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#define OAREPORTTRIG2_INVERT_A_13 (1<<13)
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#define OAREPORTTRIG2_INVERT_A_14 (1<<14)
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#define OAREPORTTRIG2_INVERT_A_15 (1<<15)
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#define OAREPORTTRIG2_INVERT_B_0 (1<<16)
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#define OAREPORTTRIG2_INVERT_B_1 (1<<17)
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#define OAREPORTTRIG2_INVERT_B_2 (1<<18)
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#define OAREPORTTRIG2_INVERT_B_3 (1<<19)
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#define OAREPORTTRIG2_INVERT_C_0 (1<<20)
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#define OAREPORTTRIG2_INVERT_C_1 (1<<21)
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#define OAREPORTTRIG2_INVERT_D_0 (1<<22)
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#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23)
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#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31)
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#define OAREPORTTRIG3 _MMIO(0x2748)
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#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
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#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
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#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
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#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
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#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
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#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
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#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
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#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
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#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
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#define OAREPORTTRIG4 _MMIO(0x274c)
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#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
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#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
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#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
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#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
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#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
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#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
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#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
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#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
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#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
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#define OAREPORTTRIG5 _MMIO(0x2750)
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#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
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#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
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#define OAREPORTTRIG6 _MMIO(0x2754)
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#define OAREPORTTRIG6_INVERT_A_0 (1<<0)
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#define OAREPORTTRIG6_INVERT_A_1 (1<<1)
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#define OAREPORTTRIG6_INVERT_A_2 (1<<2)
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#define OAREPORTTRIG6_INVERT_A_3 (1<<3)
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#define OAREPORTTRIG6_INVERT_A_4 (1<<4)
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#define OAREPORTTRIG6_INVERT_A_5 (1<<5)
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#define OAREPORTTRIG6_INVERT_A_6 (1<<6)
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#define OAREPORTTRIG6_INVERT_A_7 (1<<7)
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#define OAREPORTTRIG6_INVERT_A_8 (1<<8)
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#define OAREPORTTRIG6_INVERT_A_9 (1<<9)
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#define OAREPORTTRIG6_INVERT_A_10 (1<<10)
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#define OAREPORTTRIG6_INVERT_A_11 (1<<11)
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#define OAREPORTTRIG6_INVERT_A_12 (1<<12)
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#define OAREPORTTRIG6_INVERT_A_13 (1<<13)
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#define OAREPORTTRIG6_INVERT_A_14 (1<<14)
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#define OAREPORTTRIG6_INVERT_A_15 (1<<15)
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#define OAREPORTTRIG6_INVERT_B_0 (1<<16)
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#define OAREPORTTRIG6_INVERT_B_1 (1<<17)
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#define OAREPORTTRIG6_INVERT_B_2 (1<<18)
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#define OAREPORTTRIG6_INVERT_B_3 (1<<19)
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#define OAREPORTTRIG6_INVERT_C_0 (1<<20)
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#define OAREPORTTRIG6_INVERT_C_1 (1<<21)
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#define OAREPORTTRIG6_INVERT_D_0 (1<<22)
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#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23)
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#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31)
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#define OAREPORTTRIG7 _MMIO(0x2758)
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#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
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#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
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#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
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#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
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#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
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#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
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#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
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#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
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#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
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#define OAREPORTTRIG8 _MMIO(0x275c)
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#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
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#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
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#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
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#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
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#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
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#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
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#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
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#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
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#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
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#define OASTARTTRIG1 _MMIO(0x2710)
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#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
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#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
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#define OASTARTTRIG2 _MMIO(0x2714)
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#define OASTARTTRIG2_INVERT_A_0 (1<<0)
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#define OASTARTTRIG2_INVERT_A_1 (1<<1)
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#define OASTARTTRIG2_INVERT_A_2 (1<<2)
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#define OASTARTTRIG2_INVERT_A_3 (1<<3)
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#define OASTARTTRIG2_INVERT_A_4 (1<<4)
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#define OASTARTTRIG2_INVERT_A_5 (1<<5)
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#define OASTARTTRIG2_INVERT_A_6 (1<<6)
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#define OASTARTTRIG2_INVERT_A_7 (1<<7)
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#define OASTARTTRIG2_INVERT_A_8 (1<<8)
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#define OASTARTTRIG2_INVERT_A_9 (1<<9)
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#define OASTARTTRIG2_INVERT_A_10 (1<<10)
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#define OASTARTTRIG2_INVERT_A_11 (1<<11)
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#define OASTARTTRIG2_INVERT_A_12 (1<<12)
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#define OASTARTTRIG2_INVERT_A_13 (1<<13)
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#define OASTARTTRIG2_INVERT_A_14 (1<<14)
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#define OASTARTTRIG2_INVERT_A_15 (1<<15)
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#define OASTARTTRIG2_INVERT_B_0 (1<<16)
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#define OASTARTTRIG2_INVERT_B_1 (1<<17)
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#define OASTARTTRIG2_INVERT_B_2 (1<<18)
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#define OASTARTTRIG2_INVERT_B_3 (1<<19)
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#define OASTARTTRIG2_INVERT_C_0 (1<<20)
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#define OASTARTTRIG2_INVERT_C_1 (1<<21)
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#define OASTARTTRIG2_INVERT_D_0 (1<<22)
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#define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23)
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#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24)
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#define OASTARTTRIG2_EVENT_SELECT_0 (1<<28)
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#define OASTARTTRIG2_EVENT_SELECT_1 (1<<29)
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#define OASTARTTRIG2_EVENT_SELECT_2 (1<<30)
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#define OASTARTTRIG2_EVENT_SELECT_3 (1<<31)
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#define OASTARTTRIG3 _MMIO(0x2718)
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#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
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#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
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#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
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#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
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#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
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#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
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#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
|
||||
#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
|
||||
#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
|
||||
|
||||
#define OASTARTTRIG4 _MMIO(0x271c)
|
||||
#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
|
||||
#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
|
||||
#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
|
||||
#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
|
||||
#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
|
||||
#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
|
||||
#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
|
||||
#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
|
||||
#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
|
||||
|
||||
#define OASTARTTRIG5 _MMIO(0x2720)
|
||||
#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
|
||||
#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
|
||||
|
||||
#define OASTARTTRIG6 _MMIO(0x2724)
|
||||
#define OASTARTTRIG6_INVERT_A_0 (1<<0)
|
||||
#define OASTARTTRIG6_INVERT_A_1 (1<<1)
|
||||
#define OASTARTTRIG6_INVERT_A_2 (1<<2)
|
||||
#define OASTARTTRIG6_INVERT_A_3 (1<<3)
|
||||
#define OASTARTTRIG6_INVERT_A_4 (1<<4)
|
||||
#define OASTARTTRIG6_INVERT_A_5 (1<<5)
|
||||
#define OASTARTTRIG6_INVERT_A_6 (1<<6)
|
||||
#define OASTARTTRIG6_INVERT_A_7 (1<<7)
|
||||
#define OASTARTTRIG6_INVERT_A_8 (1<<8)
|
||||
#define OASTARTTRIG6_INVERT_A_9 (1<<9)
|
||||
#define OASTARTTRIG6_INVERT_A_10 (1<<10)
|
||||
#define OASTARTTRIG6_INVERT_A_11 (1<<11)
|
||||
#define OASTARTTRIG6_INVERT_A_12 (1<<12)
|
||||
#define OASTARTTRIG6_INVERT_A_13 (1<<13)
|
||||
#define OASTARTTRIG6_INVERT_A_14 (1<<14)
|
||||
#define OASTARTTRIG6_INVERT_A_15 (1<<15)
|
||||
#define OASTARTTRIG6_INVERT_B_0 (1<<16)
|
||||
#define OASTARTTRIG6_INVERT_B_1 (1<<17)
|
||||
#define OASTARTTRIG6_INVERT_B_2 (1<<18)
|
||||
#define OASTARTTRIG6_INVERT_B_3 (1<<19)
|
||||
#define OASTARTTRIG6_INVERT_C_0 (1<<20)
|
||||
#define OASTARTTRIG6_INVERT_C_1 (1<<21)
|
||||
#define OASTARTTRIG6_INVERT_D_0 (1<<22)
|
||||
#define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23)
|
||||
#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24)
|
||||
#define OASTARTTRIG6_EVENT_SELECT_4 (1<<28)
|
||||
#define OASTARTTRIG6_EVENT_SELECT_5 (1<<29)
|
||||
#define OASTARTTRIG6_EVENT_SELECT_6 (1<<30)
|
||||
#define OASTARTTRIG6_EVENT_SELECT_7 (1<<31)
|
||||
|
||||
#define OASTARTTRIG7 _MMIO(0x2728)
|
||||
#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
|
||||
#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
|
||||
#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
|
||||
#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
|
||||
#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
|
||||
#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
|
||||
#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
|
||||
#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
|
||||
#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
|
||||
|
||||
#define OASTARTTRIG8 _MMIO(0x272c)
|
||||
#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
|
||||
#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
|
||||
#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
|
||||
#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
|
||||
#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
|
||||
#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
|
||||
#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
|
||||
#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
|
||||
#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
|
||||
|
||||
/* CECX_0 */
|
||||
#define OACEC_COMPARE_LESS_OR_EQUAL 6
|
||||
#define OACEC_COMPARE_NOT_EQUAL 5
|
||||
#define OACEC_COMPARE_LESS_THAN 4
|
||||
#define OACEC_COMPARE_GREATER_OR_EQUAL 3
|
||||
#define OACEC_COMPARE_EQUAL 2
|
||||
#define OACEC_COMPARE_GREATER_THAN 1
|
||||
#define OACEC_COMPARE_ANY_EQUAL 0
|
||||
|
||||
#define OACEC_COMPARE_VALUE_MASK 0xffff
|
||||
#define OACEC_COMPARE_VALUE_SHIFT 3
|
||||
|
||||
#define OACEC_SELECT_NOA (0<<19)
|
||||
#define OACEC_SELECT_PREV (1<<19)
|
||||
#define OACEC_SELECT_BOOLEAN (2<<19)
|
||||
|
||||
/* CECX_1 */
|
||||
#define OACEC_MASK_MASK 0xffff
|
||||
#define OACEC_CONSIDERATIONS_MASK 0xffff
|
||||
#define OACEC_CONSIDERATIONS_SHIFT 16
|
||||
|
||||
#define OACEC0_0 _MMIO(0x2770)
|
||||
#define OACEC0_1 _MMIO(0x2774)
|
||||
#define OACEC1_0 _MMIO(0x2778)
|
||||
#define OACEC1_1 _MMIO(0x277c)
|
||||
#define OACEC2_0 _MMIO(0x2780)
|
||||
#define OACEC2_1 _MMIO(0x2784)
|
||||
#define OACEC3_0 _MMIO(0x2788)
|
||||
#define OACEC3_1 _MMIO(0x278c)
|
||||
#define OACEC4_0 _MMIO(0x2790)
|
||||
#define OACEC4_1 _MMIO(0x2794)
|
||||
#define OACEC5_0 _MMIO(0x2798)
|
||||
#define OACEC5_1 _MMIO(0x279c)
|
||||
#define OACEC6_0 _MMIO(0x27a0)
|
||||
#define OACEC6_1 _MMIO(0x27a4)
|
||||
#define OACEC7_0 _MMIO(0x27a8)
|
||||
#define OACEC7_1 _MMIO(0x27ac)
|
||||
|
||||
|
||||
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
|
||||
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
|
||||
|
|
@ -6914,6 +7251,7 @@ enum {
|
|||
# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
|
||||
|
||||
#define GEN6_UCGCTL3 _MMIO(0x9408)
|
||||
# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
|
||||
|
||||
#define GEN7_UCGCTL4 _MMIO(0x940c)
|
||||
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
|
||||
|
|
|
|||
|
|
@ -1230,6 +1230,18 @@ struct drm_i915_gem_context_param {
|
|||
__u64 value;
|
||||
};
|
||||
|
||||
enum drm_i915_oa_format {
|
||||
I915_OA_FORMAT_A13 = 1,
|
||||
I915_OA_FORMAT_A29,
|
||||
I915_OA_FORMAT_A13_B8_C8,
|
||||
I915_OA_FORMAT_B4_C8,
|
||||
I915_OA_FORMAT_A45_B8_C8,
|
||||
I915_OA_FORMAT_B4_C8_A16,
|
||||
I915_OA_FORMAT_C4_B8,
|
||||
|
||||
I915_OA_FORMAT_MAX /* non-ABI */
|
||||
};
|
||||
|
||||
enum drm_i915_perf_property_id {
|
||||
/**
|
||||
* Open the stream for a specific context handle (as used with
|
||||
|
|
@ -1238,6 +1250,32 @@ enum drm_i915_perf_property_id {
|
|||
*/
|
||||
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
|
||||
|
||||
/**
|
||||
* A value of 1 requests the inclusion of raw OA unit reports as
|
||||
* part of stream samples.
|
||||
*/
|
||||
DRM_I915_PERF_PROP_SAMPLE_OA,
|
||||
|
||||
/**
|
||||
* The value specifies which set of OA unit metrics should be
|
||||
* be configured, defining the contents of any OA unit reports.
|
||||
*/
|
||||
DRM_I915_PERF_PROP_OA_METRICS_SET,
|
||||
|
||||
/**
|
||||
* The value specifies the size and layout of OA unit reports.
|
||||
*/
|
||||
DRM_I915_PERF_PROP_OA_FORMAT,
|
||||
|
||||
/**
|
||||
* Specifying this property implicitly requests periodic OA unit
|
||||
* sampling and (at least on Haswell) the sampling frequency is derived
|
||||
* from this exponent as follows:
|
||||
*
|
||||
* 80ns * 2^(period_exponent + 1)
|
||||
*/
|
||||
DRM_I915_PERF_PROP_OA_EXPONENT,
|
||||
|
||||
DRM_I915_PERF_PROP_MAX /* non-ABI */
|
||||
};
|
||||
|
||||
|
|
@ -1257,7 +1295,23 @@ struct drm_i915_perf_open_param {
|
|||
__u64 __user properties_ptr;
|
||||
};
|
||||
|
||||
/**
|
||||
* Enable data capture for a stream that was either opened in a disabled state
|
||||
* via I915_PERF_FLAG_DISABLED or was later disabled via
|
||||
* I915_PERF_IOCTL_DISABLE.
|
||||
*
|
||||
* It is intended to be cheaper to disable and enable a stream than it may be
|
||||
* to close and re-open a stream with the same configuration.
|
||||
*
|
||||
* It's undefined whether any pending data for the stream will be lost.
|
||||
*/
|
||||
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
|
||||
|
||||
/**
|
||||
* Disable data capture for a stream.
|
||||
*
|
||||
* It is an error to try and read a stream that is disabled.
|
||||
*/
|
||||
#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
|
||||
|
||||
/**
|
||||
|
|
@ -1281,17 +1335,30 @@ enum drm_i915_perf_record_type {
|
|||
* every sample.
|
||||
*
|
||||
* The order of these sample properties given by userspace has no
|
||||
* affect on the ordering of data within a sample. The order will be
|
||||
* affect on the ordering of data within a sample. The order is
|
||||
* documented here.
|
||||
*
|
||||
* struct {
|
||||
* struct drm_i915_perf_record_header header;
|
||||
*
|
||||
* TODO: itemize extensible sample data here
|
||||
* { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
|
||||
* };
|
||||
*/
|
||||
DRM_I915_PERF_RECORD_SAMPLE = 1,
|
||||
|
||||
/*
|
||||
* Indicates that one or more OA reports were not written by the
|
||||
* hardware. This can happen for example if an MI_REPORT_PERF_COUNT
|
||||
* command collides with periodic sampling - which would be more likely
|
||||
* at higher sampling frequencies.
|
||||
*/
|
||||
DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
|
||||
|
||||
/**
|
||||
* An error occurred that resulted in all pending OA reports being lost.
|
||||
*/
|
||||
DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
|
||||
|
||||
DRM_I915_PERF_RECORD_MAX /* non-ABI */
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue