m68k: add ColdFire mcf5441x eDMA platform support
This patch adds support for ColdFire eDMA platform driver. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>hifive-unleashed-5.1
Angelo Dureghello
Greg Ungerer
parent
5908e6b738
commit
d7e9d01ac2
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@ -14,11 +14,14 @@
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <linux/fec.h>
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#include <linux/dmaengine.h>
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#include <asm/traps.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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#include <linux/platform_data/edma.h>
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#include <linux/platform_data/dma-mcf-edma.h>
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/*
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* All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
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@ -476,6 +479,81 @@ static struct platform_device mcf_i2c5 = {
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#endif /* MCFI2C_BASE5 */
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#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
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#if IS_ENABLED(CONFIG_MCF_EDMA)
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static const struct dma_slave_map mcf_edma_map[] = {
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{ "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) },
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{ "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) },
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{ "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) },
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{ "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) },
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{ "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) },
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{ "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) },
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{ "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) },
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{ "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) },
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{ "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) },
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{ "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) },
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{ "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) },
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{ "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) },
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{ "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) },
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{ "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) },
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{ "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) },
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{ "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) },
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};
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static struct mcf_edma_platform_data mcf_edma_data = {
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.dma_channels = 64,
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.slave_map = mcf_edma_map,
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.slavecnt = ARRAY_SIZE(mcf_edma_map),
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};
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static struct resource mcf_edma_resources[] = {
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{
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.start = MCFEDMA_BASE,
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.end = MCFEDMA_BASE + MCFEDMA_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCFEDMA_IRQ_INTR0,
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.end = MCFEDMA_IRQ_INTR0 + 15,
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.flags = IORESOURCE_IRQ,
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.name = "edma-tx-00-15",
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},
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{
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.start = MCFEDMA_IRQ_INTR16,
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.end = MCFEDMA_IRQ_INTR16 + 39,
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.flags = IORESOURCE_IRQ,
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.name = "edma-tx-16-55",
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},
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{
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.start = MCFEDMA_IRQ_INTR56,
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.end = MCFEDMA_IRQ_INTR56,
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.flags = IORESOURCE_IRQ,
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.name = "edma-tx-56-63",
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},
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{
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.start = MCFEDMA_IRQ_ERR,
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.end = MCFEDMA_IRQ_ERR,
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.flags = IORESOURCE_IRQ,
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.name = "edma-err",
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},
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};
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static u64 mcf_edma_dmamask = DMA_BIT_MASK(32);
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static struct platform_device mcf_edma = {
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.name = "mcf-edma",
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.id = 0,
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.num_resources = ARRAY_SIZE(mcf_edma_resources),
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.resource = mcf_edma_resources,
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.dev = {
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.dma_mask = &mcf_edma_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &mcf_edma_data,
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}
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};
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#endif /* IS_ENABLED(CONFIG_MCF_EDMA) */
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static struct platform_device *mcf_devices[] __initdata = {
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&mcf_uart,
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#if IS_ENABLED(CONFIG_FEC)
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@ -505,6 +583,9 @@ static struct platform_device *mcf_devices[] __initdata = {
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&mcf_i2c5,
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#endif
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#endif
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#if IS_ENABLED(CONFIG_MCF_EDMA)
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&mcf_edma,
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#endif
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};
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/*
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@ -137,6 +137,8 @@ struct clk *mcf_clks[] = {
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static struct clk * const enable_clks[] __initconst = {
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/* make sure these clocks are enabled */
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&__clk_0_15, /* dspi.1 */
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&__clk_0_17, /* eDMA */
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&__clk_0_18, /* intc0 */
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&__clk_0_19, /* intc0 */
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&__clk_0_20, /* intc0 */
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@ -157,8 +159,6 @@ static struct clk * const disable_clks[] __initconst = {
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&__clk_0_8, /* can.0 */
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&__clk_0_9, /* can.1 */
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&__clk_0_14, /* i2c.1 */
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&__clk_0_15, /* dspi.1 */
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&__clk_0_17, /* eDMA */
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&__clk_0_22, /* i2c.0 */
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&__clk_0_23, /* dspi.0 */
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&__clk_0_28, /* tmr.1 */
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@ -282,6 +282,21 @@
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* DSPI module.
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*/
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#define MCFDSPI_BASE0 0xfc05c000
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#define MCFDSPI_BASE1 0xfC03c000
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#define MCF_IRQ_DSPI0 (MCFINT0_VECBASE + MCFINT0_DSPI0)
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#define MCF_IRQ_DSPI1 (MCFINT1_VECBASE + MCFINT1_DSPI1)
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/*
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* eDMA module.
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*/
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#define MCFEDMA_BASE 0xfc044000
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#define MCFEDMA_SIZE 0x4000
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#define MCFINT0_EDMA_INTR0 8
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#define MCFINT0_EDMA_ERR 24
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#define MCFEDMA_EDMA_INTR16 8
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#define MCFEDMA_EDMA_INTR56 0
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#define MCFEDMA_IRQ_INTR0 (MCFINT0_VECBASE + MCFINT0_EDMA_INTR0)
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#define MCFEDMA_IRQ_INTR16 (MCFINT1_VECBASE + MCFEDMA_EDMA_INTR16)
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#define MCFEDMA_IRQ_INTR56 (MCFINT2_VECBASE + MCFEDMA_EDMA_INTR56)
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#define MCFEDMA_IRQ_ERR (MCFINT0_VECBASE + MCFINT0_EDMA_ERR)
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#endif /* m5441xsim_h */
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