Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (27 commits) Blackfin: fix dma-mapping build errors Blackfin: hook up new perf_counter_open syscall Blackfin: drop BF535-specific text for exception 0x2A (unaligned instruction) Blackfin: fix early crash when booting on wrong cpu Blackfin: fix GPTMR0_CLOCKSOURCE dependency on BFIN_GPTIMERS Blackfin: drop unused ISP1760 port1_disable from board resources Blackfin: bf526-ezbrd: handle different SDRAM chips Blackfin: fix typo in TRAS define in mem_init.h header Blackfin: unify memory map headers Blackfin: stick the CPU name into boot image name Blackfin: update defconfigs Blackfin: decouple unrelated cache settings to get exact behavior Blackfin: update I-pipe patch level Blackfin: remove obsolete mcount support from I-pipe code Blackfin: allow CONFIG_TICKSOURCE_GPTMR0 with interrupt pipeline Blackfin: convert interrupt pipeline to irqflags Blackfin: allow people to select BF51x-0.1 silicon rev Blackfin: bf526-ezbrd: set SPI flash resources to SST device Blackfin: fix accidental reset in some boot modes Blackfin: abstract irq14 lowering in do_irq ...
This commit is contained in:
commit
d888a4c76c
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@ -274,7 +274,7 @@ config BF_REV_0_0
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|||
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config BF_REV_0_1
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bool "0.1"
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depends on (BF52x || (BF54x && !BF54xM))
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depends on (BF51x || BF52x || (BF54x && !BF54xM))
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||||
config BF_REV_0_2
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bool "0.2"
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|
@ -358,7 +358,7 @@ config MEM_MT48LC8M32B2B5_7
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config MEM_MT48LC32M16A2TG_75
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bool
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depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
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depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
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default y
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config MEM_MT48LC32M8A2_75
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|
@ -366,6 +366,11 @@ config MEM_MT48LC32M8A2_75
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depends on (BFIN518F_EZBRD)
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default y
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config MEM_MT48H32M16LFCJ_75
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bool
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depends on (BFIN526_EZBRD)
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default y
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source "arch/blackfin/mach-bf518/Kconfig"
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source "arch/blackfin/mach-bf527/Kconfig"
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source "arch/blackfin/mach-bf533/Kconfig"
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@ -623,7 +628,6 @@ choice
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config TICKSOURCE_GPTMR0
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bool "Gptimer0 (SCLK domain)"
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select BFIN_GPTIMERS
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depends on !IPIPE
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config TICKSOURCE_CORETMR
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bool "Core timer (CCLK domain)"
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|
@ -644,6 +648,7 @@ config CYCLES_CLOCKSOURCE
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config GPTMR0_CLOCKSOURCE
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bool "Use GPTimer0 as a clocksource (higher rating)"
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select BFIN_GPTIMERS
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depends on GENERIC_CLOCKEVENTS
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depends on !TICKSOURCE_GPTMR0
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@ -908,76 +913,97 @@ endchoice
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comment "Cache Support"
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config BFIN_ICACHE
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bool "Enable ICACHE"
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default y
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config BFIN_ICACHE_LOCK
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bool "Enable Instruction Cache Locking"
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depends on BFIN_ICACHE
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default n
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config BFIN_EXTMEM_ICACHEABLE
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bool "Enable ICACHE for external memory"
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depends on BFIN_ICACHE
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default y
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config BFIN_L2_ICACHEABLE
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bool "Enable ICACHE for L2 SRAM"
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depends on BFIN_ICACHE
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depends on BF54x || BF561
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default n
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config BFIN_DCACHE
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bool "Enable DCACHE"
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default y
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config BFIN_DCACHE_BANKA
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bool "Enable only 16k BankA DCACHE - BankB is SRAM"
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depends on BFIN_DCACHE && !BF531
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default n
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config BFIN_ICACHE_LOCK
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bool "Enable Instruction Cache Locking"
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choice
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prompt "External memory cache policy"
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config BFIN_EXTMEM_DCACHEABLE
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bool "Enable DCACHE for external memory"
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depends on BFIN_DCACHE
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default BFIN_WB if !SMP
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default BFIN_WT if SMP
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config BFIN_WB
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bool "Write back"
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depends on !SMP
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help
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Write Back Policy:
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Cached data will be written back to SDRAM only when needed.
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This can give a nice increase in performance, but beware of
|
||||
broken drivers that do not properly invalidate/flush their
|
||||
cache.
|
||||
|
||||
Write Through Policy:
|
||||
Cached data will always be written back to SDRAM when the
|
||||
cache is updated. This is a completely safe setting, but
|
||||
performance is worse than Write Back.
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||||
|
||||
If you are unsure of the options and you want to be safe,
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||||
then go with Write Through.
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|
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config BFIN_WT
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bool "Write through"
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help
|
||||
Write Back Policy:
|
||||
Cached data will be written back to SDRAM only when needed.
|
||||
This can give a nice increase in performance, but beware of
|
||||
broken drivers that do not properly invalidate/flush their
|
||||
cache.
|
||||
|
||||
Write Through Policy:
|
||||
Cached data will always be written back to SDRAM when the
|
||||
cache is updated. This is a completely safe setting, but
|
||||
performance is worse than Write Back.
|
||||
|
||||
If you are unsure of the options and you want to be safe,
|
||||
then go with Write Through.
|
||||
|
||||
endchoice
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||||
|
||||
default y
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choice
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prompt "L2 SRAM cache policy"
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depends on (BF54x || BF561)
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default BFIN_L2_WT
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config BFIN_L2_WB
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prompt "External memory DCACHE policy"
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depends on BFIN_EXTMEM_DCACHEABLE
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default BFIN_EXTMEM_WRITEBACK if !SMP
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default BFIN_EXTMEM_WRITETHROUGH if SMP
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config BFIN_EXTMEM_WRITEBACK
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bool "Write back"
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depends on !SMP
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||||
help
|
||||
Write Back Policy:
|
||||
Cached data will be written back to SDRAM only when needed.
|
||||
This can give a nice increase in performance, but beware of
|
||||
broken drivers that do not properly invalidate/flush their
|
||||
cache.
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||||
|
||||
config BFIN_L2_WT
|
||||
Write Through Policy:
|
||||
Cached data will always be written back to SDRAM when the
|
||||
cache is updated. This is a completely safe setting, but
|
||||
performance is worse than Write Back.
|
||||
|
||||
If you are unsure of the options and you want to be safe,
|
||||
then go with Write Through.
|
||||
|
||||
config BFIN_EXTMEM_WRITETHROUGH
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||||
bool "Write through"
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||||
depends on !SMP
|
||||
help
|
||||
Write Back Policy:
|
||||
Cached data will be written back to SDRAM only when needed.
|
||||
This can give a nice increase in performance, but beware of
|
||||
broken drivers that do not properly invalidate/flush their
|
||||
cache.
|
||||
|
||||
config BFIN_L2_NOT_CACHED
|
||||
bool "Not cached"
|
||||
Write Through Policy:
|
||||
Cached data will always be written back to SDRAM when the
|
||||
cache is updated. This is a completely safe setting, but
|
||||
performance is worse than Write Back.
|
||||
|
||||
If you are unsure of the options and you want to be safe,
|
||||
then go with Write Through.
|
||||
|
||||
endchoice
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||||
|
||||
config BFIN_L2_DCACHEABLE
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bool "Enable DCACHE for L2 SRAM"
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||||
depends on BFIN_DCACHE
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||||
depends on BF54x || BF561
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||||
default n
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||||
choice
|
||||
prompt "L2 SRAM DCACHE policy"
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||||
depends on BFIN_L2_DCACHEABLE
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||||
default BFIN_L2_WRITEBACK
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||||
config BFIN_L2_WRITEBACK
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bool "Write back"
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depends on !SMP
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||||
|
||||
config BFIN_L2_WRITETHROUGH
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||||
bool "Write through"
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||||
depends on !SMP
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||||
endchoice
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||||
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||||
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||||
comment "Memory Protection Unit"
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||||
config MPU
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||||
bool "Enable the memory protection unit (EXPERIMENTAL)"
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||||
default n
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||||
|
|
|
@ -13,7 +13,7 @@ extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma
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|||
|
||||
quiet_cmd_uimage = UIMAGE $@
|
||||
cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
|
||||
-C $(2) -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
|
||||
-C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
|
||||
-e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
|
||||
-d $< $@
|
||||
|
||||
|
|
|
@ -326,11 +326,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
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||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
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||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
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||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
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||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
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||||
|
||||
#
|
||||
# Memory Protection Unit
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||||
#
|
||||
# CONFIG_MPU is not set
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||||
|
||||
#
|
||||
|
@ -413,11 +419,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
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||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
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||||
|
@ -916,7 +922,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
|
|||
# CONFIG_MMC_SDHCI is not set
|
||||
CONFIG_SDH_BFIN=m
|
||||
CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
|
||||
CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ=y
|
||||
# CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set
|
||||
# CONFIG_MMC_SPI is not set
|
||||
# CONFIG_MEMSTICK is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
|
@ -1147,7 +1153,7 @@ CONFIG_SCHED_DEBUG=y
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|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -331,16 +331,18 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_MPU is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Asynchonous Memory Configuration
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
# EBIU_AMGCTL Global Control
|
||||
|
@ -418,11 +420,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1424,7 +1426,7 @@ CONFIG_SCHED_DEBUG=y
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -331,11 +331,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -418,11 +424,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1505,7 +1511,7 @@ CONFIG_SCHED_DEBUG=y
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -289,15 +289,24 @@ CONFIG_BFIN_GPTIMERS=m
|
|||
CONFIG_DMA_UNCACHED_1M=y
|
||||
# CONFIG_DMA_UNCACHED_NONE is not set
|
||||
|
||||
#
|
||||
# Cache Support
|
||||
#
|
||||
#
|
||||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -391,11 +400,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1052,7 +1061,7 @@ CONFIG_SCHED_DEBUG=y
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -293,11 +293,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -391,11 +397,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1216,7 +1222,7 @@ CONFIG_SCHED_DEBUG=y
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -300,11 +300,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -399,11 +405,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1269,7 +1275,7 @@ CONFIG_SCHED_DEBUG=y
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -311,11 +311,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -398,11 +404,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1203,7 +1209,7 @@ CONFIG_SCHED_DEBUG=y
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -366,14 +366,19 @@ CONFIG_DMA_UNCACHED_2M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_BFIN_L2_WB is not set
|
||||
CONFIG_BFIN_L2_WT=y
|
||||
# CONFIG_BFIN_L2_NOT_CACHED is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
# CONFIG_BFIN_L2_ICACHEABLE is not set
|
||||
# CONFIG_BFIN_L2_DCACHEABLE is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -459,11 +464,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1606,7 +1611,7 @@ CONFIG_SCHED_DEBUG=y
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -331,14 +331,19 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
# CONFIG_BFIN_L2_WB is not set
|
||||
CONFIG_BFIN_L2_WT=y
|
||||
# CONFIG_BFIN_L2_NOT_CACHED is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
# CONFIG_BFIN_L2_ICACHEABLE is not set
|
||||
# CONFIG_BFIN_L2_DCACHEABLE is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -425,11 +430,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1044,7 +1049,7 @@ CONFIG_SCHED_DEBUG=y
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -285,11 +285,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
|
|
@ -329,11 +329,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -417,11 +423,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1246,7 +1252,7 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
|
|||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_DEBUG_INFO is not set
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
|
|
|
@ -262,12 +262,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_L1_MAX_PIECE=16
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -353,10 +358,10 @@ CONFIG_IP_FIB_HASH=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -873,7 +878,7 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_MMRS=y
|
||||
CONFIG_DEBUG_HUNT_FOR_ZERO=y
|
||||
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
|
||||
|
|
|
@ -297,11 +297,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -383,11 +389,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -861,7 +867,7 @@ CONFIG_DEBUG_FS=y
|
|||
# CONFIG_HEADERS_CHECK is not set
|
||||
CONFIG_DEBUG_SECTION_MISMATCH=y
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_DEBUG_MEMORY_INIT is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
|
||||
|
|
|
@ -270,12 +270,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_L1_MAX_PIECE=16
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -361,10 +366,10 @@ CONFIG_IP_FIB_HASH=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -901,7 +906,7 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_MMRS=y
|
||||
CONFIG_DEBUG_HUNT_FOR_ZERO=y
|
||||
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
|
||||
|
|
|
@ -333,12 +333,19 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_L1_MAX_PIECE=16
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
# CONFIG_BFIN_L2_ICACHEABLE is not set
|
||||
# CONFIG_BFIN_L2_DCACHEABLE is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -428,11 +435,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -1334,7 +1341,7 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_DEBUG_MMRS=y
|
||||
CONFIG_DEBUG_HUNT_FOR_ZERO=y
|
||||
|
|
|
@ -308,12 +308,19 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_L1_MAX_PIECE=16
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
# CONFIG_BFIN_L2_ICACHEABLE is not set
|
||||
# CONFIG_BFIN_L2_DCACHEABLE is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -395,11 +402,11 @@ CONFIG_IP_FIB_HASH=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
@ -837,7 +844,7 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_DEBUG_MMRS=y
|
||||
CONFIG_DEBUG_HUNT_FOR_ZERO=y
|
||||
|
|
|
@ -258,12 +258,18 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
CONFIG_BFIN_ICACHE_LOCK=y
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_L1_MAX_PIECE=16
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
# Asynchonous Memory Configuration
|
||||
|
|
|
@ -295,11 +295,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -382,11 +388,11 @@ CONFIG_IP_PNP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
|
|
|
@ -279,12 +279,18 @@ CONFIG_DMA_UNCACHED_2M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_L1_MAX_PIECE=16
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
# Asynchonous Memory Configuration
|
||||
|
|
|
@ -287,11 +287,17 @@ CONFIG_DMA_UNCACHED_1M=y
|
|||
# Cache Support
|
||||
#
|
||||
CONFIG_BFIN_ICACHE=y
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_DCACHE=y
|
||||
# CONFIG_BFIN_DCACHE_BANKA is not set
|
||||
# CONFIG_BFIN_ICACHE_LOCK is not set
|
||||
CONFIG_BFIN_WB=y
|
||||
# CONFIG_BFIN_WT is not set
|
||||
CONFIG_BFIN_EXTMEM_ICACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_DCACHEABLE=y
|
||||
CONFIG_BFIN_EXTMEM_WRITEBACK=y
|
||||
# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
|
||||
|
||||
#
|
||||
# Memory Protection Unit
|
||||
#
|
||||
# CONFIG_MPU is not set
|
||||
|
||||
#
|
||||
|
@ -709,7 +715,7 @@ CONFIG_FRAME_WARN=1024
|
|||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_DEBUG_MEMORY_INIT is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
|
||||
|
|
|
@ -86,6 +86,7 @@ static inline void CSYNC(void)
|
|||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#include <asm/mem_map.h>
|
||||
#include <mach/blackfin.h>
|
||||
#include <asm/bfin-global.h>
|
||||
|
||||
|
|
|
@ -35,10 +35,10 @@
|
|||
|
||||
#if defined(CONFIG_SMP) && \
|
||||
!defined(CONFIG_BFIN_CACHE_COHERENT)
|
||||
# if defined(CONFIG_BFIN_ICACHE)
|
||||
# if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
|
||||
# define __ARCH_SYNC_CORE_ICACHE
|
||||
# endif
|
||||
# if defined(CONFIG_BFIN_DCACHE)
|
||||
# if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
|
||||
# define __ARCH_SYNC_CORE_DCACHE
|
||||
# endif
|
||||
#ifndef __ASSEMBLY__
|
||||
|
|
|
@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void);
|
|||
|
||||
static inline void flush_icache_range(unsigned start, unsigned end)
|
||||
{
|
||||
#if defined(CONFIG_BFIN_WB)
|
||||
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
|
||||
blackfin_dcache_flush_range(start, end);
|
||||
#endif
|
||||
|
||||
|
@ -87,9 +87,9 @@ do { memcpy(dst, src, len); \
|
|||
#else
|
||||
# define invalidate_dcache_range(start,end) do { } while (0)
|
||||
#endif
|
||||
#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
|
||||
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
|
||||
# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
|
||||
# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
|
||||
# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
|
||||
#else
|
||||
# define flush_dcache_range(start,end) do { } while (0)
|
||||
# define flush_dcache_page(page) do { } while (0)
|
||||
|
@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on;
|
|||
|
||||
static inline int bfin_addr_dcacheable(unsigned long addr)
|
||||
{
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
|
||||
if (addr < (_ramend - DMA_UNCACHED_REGION))
|
||||
return 1;
|
||||
#endif
|
||||
|
@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr)
|
|||
addr >= _ramend && addr < physical_mem_end)
|
||||
return 1;
|
||||
|
||||
#ifndef CONFIG_BFIN_L2_NOT_CACHED
|
||||
#ifdef CONFIG_BFIN_L2_DCACHEABLE
|
||||
if (addr >= L2_START && addr < L2_START + L2_LENGTH)
|
||||
return 1;
|
||||
#endif
|
||||
|
|
|
@ -37,8 +37,6 @@
|
|||
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
|
||||
|
||||
#if ANOMALY_05000158
|
||||
#define ANOMALY_05000158_WORKAROUND 0x200
|
||||
#else
|
||||
|
@ -47,10 +45,12 @@
|
|||
|
||||
#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
|
||||
#ifdef CONFIG_BFIN_WB /*Write Back Policy */
|
||||
#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
|
||||
#else /*Write Through */
|
||||
#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
|
||||
#else
|
||||
#define SDRAM_DGENERIC (CPLB_COMMON)
|
||||
#endif
|
||||
|
||||
#define SDRAM_DNON_CHBL (CPLB_COMMON)
|
||||
|
@ -61,21 +61,23 @@
|
|||
|
||||
#ifdef CONFIG_SMP
|
||||
#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
|
||||
#define L2_IMEMORY (CPLB_COMMON)
|
||||
#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON)
|
||||
#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
|
||||
#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
|
||||
|
||||
#else
|
||||
#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
|
||||
#define L2_IMEMORY (SDRAM_IGENERIC)
|
||||
|
||||
# if defined(CONFIG_BFIN_L2_WB)
|
||||
# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON)
|
||||
# elif defined(CONFIG_BFIN_L2_WT)
|
||||
# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
|
||||
# elif defined(CONFIG_BFIN_L2_NOT_CACHED)
|
||||
# define L2_DMEMORY (CPLB_COMMON)
|
||||
# if defined(CONFIG_BFIN_L2_ICACHEABLE)
|
||||
# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
|
||||
# else
|
||||
# define L2_DMEMORY (0)
|
||||
# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
|
||||
# endif
|
||||
|
||||
# if defined(CONFIG_BFIN_L2_WRITEBACK)
|
||||
# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
|
||||
# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
|
||||
# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
|
||||
# else
|
||||
# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
|
||||
# endif
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
|
|
|
@ -95,4 +95,17 @@ static inline void dma_sync_single_for_device(struct device *dev,
|
|||
enum dma_data_direction dir)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void dma_sync_sg_for_cpu(struct device *dev,
|
||||
struct scatterlist *sg,
|
||||
int nents, enum dma_data_direction dir)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void dma_sync_sg_for_device(struct device *dev,
|
||||
struct scatterlist *sg,
|
||||
int nents, enum dma_data_direction dir)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* _BLACKFIN_DMA_MAPPING_H */
|
||||
|
|
|
@ -35,9 +35,9 @@
|
|||
#include <asm/atomic.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
#define IPIPE_ARCH_STRING "1.10-00"
|
||||
#define IPIPE_ARCH_STRING "1.11-00"
|
||||
#define IPIPE_MAJOR_NUMBER 1
|
||||
#define IPIPE_MINOR_NUMBER 10
|
||||
#define IPIPE_MINOR_NUMBER 11
|
||||
#define IPIPE_PATCH_NUMBER 0
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
@ -207,7 +207,7 @@ void ipipe_init_irq_threads(void);
|
|||
|
||||
int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
|
||||
|
||||
#ifdef CONFIG_GENERIC_CLOCKEVENTS
|
||||
#ifdef CONFIG_TICKSOURCE_CORETMR
|
||||
#define IRQ_SYSTMR IRQ_CORETMR
|
||||
#define IRQ_PRIOTMR IRQ_CORETMR
|
||||
#else
|
||||
|
@ -240,8 +240,13 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
|
|||
#define ipipe_init_irq_threads() do { } while (0)
|
||||
#define ipipe_start_irq_thread(irq, desc) 0
|
||||
|
||||
#ifndef CONFIG_TICKSOURCE_GPTMR0
|
||||
#define IRQ_SYSTMR IRQ_CORETMR
|
||||
#define IRQ_PRIOTMR IRQ_CORETMR
|
||||
#else
|
||||
#define IRQ_SYSTMR IRQ_TIMER0
|
||||
#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
|
||||
#endif
|
||||
|
||||
#define __ipipe_root_tick_p(regs) 1
|
||||
|
||||
|
|
|
@ -51,23 +51,23 @@
|
|||
|
||||
extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
|
||||
|
||||
static inline void __ipipe_stall_root(void)
|
||||
{
|
||||
volatile unsigned long *p = &__ipipe_root_status;
|
||||
set_bit(0, p);
|
||||
}
|
||||
#define __ipipe_stall_root() \
|
||||
do { \
|
||||
volatile unsigned long *p = &__ipipe_root_status; \
|
||||
set_bit(0, p); \
|
||||
} while (0)
|
||||
|
||||
static inline unsigned long __ipipe_test_and_stall_root(void)
|
||||
{
|
||||
volatile unsigned long *p = &__ipipe_root_status;
|
||||
return test_and_set_bit(0, p);
|
||||
}
|
||||
#define __ipipe_test_and_stall_root() \
|
||||
({ \
|
||||
volatile unsigned long *p = &__ipipe_root_status; \
|
||||
test_and_set_bit(0, p); \
|
||||
})
|
||||
|
||||
static inline unsigned long __ipipe_test_root(void)
|
||||
{
|
||||
const unsigned long *p = &__ipipe_root_status;
|
||||
return test_bit(0, p);
|
||||
}
|
||||
#define __ipipe_test_root() \
|
||||
({ \
|
||||
const unsigned long *p = &__ipipe_root_status; \
|
||||
test_bit(0, p); \
|
||||
})
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
|
|
|
@ -22,13 +22,6 @@
|
|||
/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
|
||||
#include <mach/irq.h>
|
||||
|
||||
/* Xenomai IPIPE helpers */
|
||||
#define local_irq_restore_hw(x) local_irq_restore(x)
|
||||
#define local_irq_save_hw(x) local_irq_save(x)
|
||||
#define local_irq_enable_hw(x) local_irq_enable(x)
|
||||
#define local_irq_disable_hw(x) local_irq_disable(x)
|
||||
#define irqs_disabled_hw(x) irqs_disabled(x)
|
||||
|
||||
#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
|
||||
# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
|
||||
#else
|
||||
|
|
|
@ -31,6 +31,150 @@ static inline unsigned long bfin_cli(void)
|
|||
return flags;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IPIPE
|
||||
|
||||
#include <linux/ipipe_base.h>
|
||||
#include <linux/ipipe_trace.h>
|
||||
|
||||
#ifdef CONFIG_DEBUG_HWERR
|
||||
# define bfin_no_irqs 0x3f
|
||||
#else
|
||||
# define bfin_no_irqs 0x1f
|
||||
#endif
|
||||
|
||||
#define raw_local_irq_disable() \
|
||||
do { \
|
||||
ipipe_check_context(ipipe_root_domain); \
|
||||
__ipipe_stall_root(); \
|
||||
barrier(); \
|
||||
} while (0)
|
||||
|
||||
static inline void raw_local_irq_enable(void)
|
||||
{
|
||||
barrier();
|
||||
ipipe_check_context(ipipe_root_domain);
|
||||
__ipipe_unstall_root();
|
||||
}
|
||||
|
||||
#define raw_local_save_flags_ptr(x) \
|
||||
do { \
|
||||
*(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \
|
||||
} while (0)
|
||||
|
||||
#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x))
|
||||
|
||||
#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs)
|
||||
|
||||
#define raw_local_irq_save_ptr(x) \
|
||||
do { \
|
||||
*(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \
|
||||
barrier(); \
|
||||
} while (0)
|
||||
|
||||
#define raw_local_irq_save(x) \
|
||||
do { \
|
||||
ipipe_check_context(ipipe_root_domain); \
|
||||
raw_local_irq_save_ptr(&(x)); \
|
||||
} while (0)
|
||||
|
||||
static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
|
||||
{
|
||||
/*
|
||||
* Merge virtual and real interrupt mask bits into a single
|
||||
* 32bit word.
|
||||
*/
|
||||
return (real & ~(1 << 31)) | ((virt != 0) << 31);
|
||||
}
|
||||
|
||||
static inline int raw_demangle_irq_bits(unsigned long *x)
|
||||
{
|
||||
int virt = (*x & (1 << 31)) != 0;
|
||||
*x &= ~(1L << 31);
|
||||
return virt;
|
||||
}
|
||||
|
||||
static inline void local_irq_disable_hw_notrace(void)
|
||||
{
|
||||
bfin_cli();
|
||||
}
|
||||
|
||||
static inline void local_irq_enable_hw_notrace(void)
|
||||
{
|
||||
bfin_sti(bfin_irq_flags);
|
||||
}
|
||||
|
||||
#define local_save_flags_hw(flags) \
|
||||
do { \
|
||||
(flags) = bfin_read_IMASK(); \
|
||||
} while (0)
|
||||
|
||||
#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0)
|
||||
|
||||
#define irqs_disabled_hw() \
|
||||
({ \
|
||||
unsigned long flags; \
|
||||
local_save_flags_hw(flags); \
|
||||
irqs_disabled_flags_hw(flags); \
|
||||
})
|
||||
|
||||
static inline void local_irq_save_ptr_hw(unsigned long *flags)
|
||||
{
|
||||
*flags = bfin_cli();
|
||||
#ifdef CONFIG_DEBUG_HWERR
|
||||
bfin_sti(0x3f);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define local_irq_save_hw_notrace(flags) \
|
||||
do { \
|
||||
local_irq_save_ptr_hw(&(flags)); \
|
||||
} while (0)
|
||||
|
||||
static inline void local_irq_restore_hw_notrace(unsigned long flags)
|
||||
{
|
||||
if (!irqs_disabled_flags_hw(flags))
|
||||
local_irq_enable_hw_notrace();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
|
||||
# define local_irq_disable_hw() \
|
||||
do { \
|
||||
if (!irqs_disabled_hw()) { \
|
||||
local_irq_disable_hw_notrace(); \
|
||||
ipipe_trace_begin(0x80000000); \
|
||||
} \
|
||||
} while (0)
|
||||
# define local_irq_enable_hw() \
|
||||
do { \
|
||||
if (irqs_disabled_hw()) { \
|
||||
ipipe_trace_end(0x80000000); \
|
||||
local_irq_enable_hw_notrace(); \
|
||||
} \
|
||||
} while (0)
|
||||
# define local_irq_save_hw(flags) \
|
||||
do { \
|
||||
local_save_flags_hw(flags); \
|
||||
if (!irqs_disabled_flags_hw(flags)) { \
|
||||
local_irq_disable_hw_notrace(); \
|
||||
ipipe_trace_begin(0x80000001); \
|
||||
} \
|
||||
} while (0)
|
||||
# define local_irq_restore_hw(flags) \
|
||||
do { \
|
||||
if (!irqs_disabled_flags_hw(flags)) { \
|
||||
ipipe_trace_end(0x80000001); \
|
||||
local_irq_enable_hw_notrace(); \
|
||||
} \
|
||||
} while (0)
|
||||
#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
|
||||
# define local_irq_disable_hw() local_irq_disable_hw_notrace()
|
||||
# define local_irq_enable_hw() local_irq_enable_hw_notrace()
|
||||
# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags)
|
||||
# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags)
|
||||
#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
|
||||
|
||||
#else /* CONFIG_IPIPE */
|
||||
|
||||
static inline void raw_local_irq_disable(void)
|
||||
{
|
||||
bfin_cli();
|
||||
|
@ -44,12 +188,6 @@ static inline void raw_local_irq_enable(void)
|
|||
|
||||
#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0)
|
||||
|
||||
static inline void raw_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
if (!raw_irqs_disabled_flags(flags))
|
||||
raw_local_irq_enable();
|
||||
}
|
||||
|
||||
static inline unsigned long __raw_local_irq_save(void)
|
||||
{
|
||||
unsigned long flags = bfin_cli();
|
||||
|
@ -60,4 +198,18 @@ static inline unsigned long __raw_local_irq_save(void)
|
|||
}
|
||||
#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0)
|
||||
|
||||
#define local_irq_save_hw(flags) raw_local_irq_save(flags)
|
||||
#define local_irq_restore_hw(flags) raw_local_irq_restore(flags)
|
||||
#define local_irq_enable_hw() raw_local_irq_enable()
|
||||
#define local_irq_disable_hw() raw_local_irq_disable()
|
||||
#define irqs_disabled_hw() irqs_disabled()
|
||||
|
||||
#endif /* !CONFIG_IPIPE */
|
||||
|
||||
static inline void raw_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
if (!raw_irqs_disabled_flags(flags))
|
||||
raw_local_irq_enable();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -59,7 +59,7 @@
|
|||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_4
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRAS_num 4
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
|
@ -89,6 +89,85 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The BF526-EZ-Board changed SDRAM chips between revisions,
|
||||
* so we use below timings to accommodate both.
|
||||
*/
|
||||
#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
|
||||
#if (CONFIG_SCLK_HZ > 119402985)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_8
|
||||
#define SDRAM_tRAS_num 8
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_7
|
||||
#define SDRAM_tRAS_num 7
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_6
|
||||
#define SDRAM_tRAS_num 6
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_5
|
||||
#define SDRAM_tRAS_num 5
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_4
|
||||
#define SDRAM_tRAS_num 4
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_4
|
||||
#define SDRAM_tRAS_num 4
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_3
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_3
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if (CONFIG_SCLK_HZ <= 29850746)
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_2
|
||||
#define SDRAM_tRAS_num 2
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
|
||||
defined(CONFIG_MEM_MT48LC8M32B2B5_7)
|
||||
/*SDRAM INFORMATION: */
|
||||
|
@ -109,6 +188,13 @@
|
|||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_2
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
|
||||
/* Equation from section 17 (p17-46) of BF533 HRM */
|
||||
|
|
|
@ -1,87 +1,84 @@
|
|||
/*
|
||||
* mem_map.h
|
||||
* Common header file for blackfin family of processors.
|
||||
* Common Blackfin memory map
|
||||
*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_H_
|
||||
#define _MEM_MAP_H_
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
#define __BFIN_MEM_MAP_H__
|
||||
|
||||
#include <mach/mem_map.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* Every Blackfin so far has MMRs like this */
|
||||
#ifndef COREMMR_BASE
|
||||
# define COREMMR_BASE 0xFFE00000
|
||||
#endif
|
||||
#ifndef SYSMMR_BASE
|
||||
# define SYSMMR_BASE 0xFFC00000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static inline ulong get_l1_scratch_start_cpu(int cpu)
|
||||
{
|
||||
return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
|
||||
}
|
||||
static inline ulong get_l1_code_start_cpu(int cpu)
|
||||
{
|
||||
return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START;
|
||||
}
|
||||
static inline ulong get_l1_data_a_start_cpu(int cpu)
|
||||
{
|
||||
return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
|
||||
}
|
||||
static inline ulong get_l1_data_b_start_cpu(int cpu)
|
||||
{
|
||||
return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
|
||||
}
|
||||
/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
|
||||
#ifndef L1_SCRATCH_START
|
||||
# define L1_SCRATCH_START 0xFFB00000
|
||||
# define L1_SCRATCH_LENGTH 0x1000
|
||||
#endif
|
||||
|
||||
static inline ulong get_l1_scratch_start(void)
|
||||
{
|
||||
return get_l1_scratch_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline ulong get_l1_code_start(void)
|
||||
{
|
||||
return get_l1_code_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline ulong get_l1_data_a_start(void)
|
||||
{
|
||||
return get_l1_data_a_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline ulong get_l1_data_b_start(void)
|
||||
{
|
||||
return get_l1_data_b_start_cpu(blackfin_core_id());
|
||||
}
|
||||
/* Most parts lack on-chip L2 SRAM */
|
||||
#ifndef L2_START
|
||||
# define L2_START 0
|
||||
# define L2_LENGTH 0
|
||||
#endif
|
||||
|
||||
#else /* !CONFIG_SMP */
|
||||
/* Most parts lack on-chip L1 ROM */
|
||||
#ifndef L1_ROM_START
|
||||
# define L1_ROM_START 0
|
||||
# define L1_ROM_LENGTH 0
|
||||
#endif
|
||||
|
||||
static inline ulong get_l1_scratch_start_cpu(int cpu)
|
||||
/* Allow wonky SMP ports to override this */
|
||||
#ifndef GET_PDA_SAFE
|
||||
# define GET_PDA_SAFE(preg) \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda;
|
||||
# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
||||
|
||||
# ifndef __ASSEMBLY__
|
||||
|
||||
static inline unsigned long get_l1_scratch_start_cpu(int cpu)
|
||||
{
|
||||
return L1_SCRATCH_START;
|
||||
}
|
||||
static inline ulong get_l1_code_start_cpu(int cpu)
|
||||
static inline unsigned long get_l1_code_start_cpu(int cpu)
|
||||
{
|
||||
return L1_CODE_START;
|
||||
}
|
||||
static inline ulong get_l1_data_a_start_cpu(int cpu)
|
||||
static inline unsigned long get_l1_data_a_start_cpu(int cpu)
|
||||
{
|
||||
return L1_DATA_A_START;
|
||||
}
|
||||
static inline ulong get_l1_data_b_start_cpu(int cpu)
|
||||
static inline unsigned long get_l1_data_b_start_cpu(int cpu)
|
||||
{
|
||||
return L1_DATA_B_START;
|
||||
}
|
||||
static inline ulong get_l1_scratch_start(void)
|
||||
static inline unsigned long get_l1_scratch_start(void)
|
||||
{
|
||||
return get_l1_scratch_start_cpu(0);
|
||||
}
|
||||
static inline ulong get_l1_code_start(void)
|
||||
static inline unsigned long get_l1_code_start(void)
|
||||
{
|
||||
return get_l1_code_start_cpu(0);
|
||||
}
|
||||
static inline ulong get_l1_data_a_start(void)
|
||||
static inline unsigned long get_l1_data_a_start(void)
|
||||
{
|
||||
return get_l1_data_a_start_cpu(0);
|
||||
}
|
||||
static inline ulong get_l1_data_b_start(void)
|
||||
static inline unsigned long get_l1_data_b_start(void)
|
||||
{
|
||||
return get_l1_data_b_start_cpu(0);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
# endif /* __ASSEMBLY__ */
|
||||
#endif /* !GET_PDA_SAFE */
|
||||
|
||||
#endif /* _MEM_MAP_H_ */
|
||||
#endif
|
||||
|
|
|
@ -135,11 +135,13 @@ struct __xchg_dummy {
|
|||
};
|
||||
#define __xg(x) ((volatile struct __xchg_dummy *)(x))
|
||||
|
||||
#include <mach/blackfin.h>
|
||||
|
||||
static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
|
||||
int size)
|
||||
{
|
||||
unsigned long tmp = 0;
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
|
||||
|
|
|
@ -111,9 +111,7 @@
|
|||
level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
|
||||
#define EXC_0x2A(level) \
|
||||
"Instruction fetch misaligned address violation\n" \
|
||||
level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
|
||||
level " exception, the return address provided in RETX is the destination address which is\n" \
|
||||
level " misaligned, rather than the address of the offending instruction.\n"
|
||||
level " - Attempted misaligned instruction cache fetch.\n"
|
||||
#define EXC_0x2B(level) \
|
||||
"CPLB protection violation\n" \
|
||||
level " - Illegal instruction fetch access (memory protection violation).\n"
|
||||
|
|
|
@ -265,4 +265,26 @@ __clear_user(void *to, unsigned long n)
|
|||
|
||||
#define clear_user(to, n) __clear_user(to, n)
|
||||
|
||||
/* How to interpret these return values:
|
||||
* CORE: can be accessed by core load or dma memcpy
|
||||
* CORE_ONLY: can only be accessed by core load
|
||||
* DMA: can only be accessed by dma memcpy
|
||||
* IDMA: can only be accessed by interprocessor dma memcpy (BF561)
|
||||
* ITEST: can be accessed by isram memcpy or dma memcpy
|
||||
*/
|
||||
enum {
|
||||
BFIN_MEM_ACCESS_CORE = 0,
|
||||
BFIN_MEM_ACCESS_CORE_ONLY,
|
||||
BFIN_MEM_ACCESS_DMA,
|
||||
BFIN_MEM_ACCESS_IDMA,
|
||||
BFIN_MEM_ACCESS_ITEST,
|
||||
};
|
||||
/**
|
||||
* bfin_mem_access_type() - what kind of memory access is required
|
||||
* @addr: the address to check
|
||||
* @size: number of bytes needed
|
||||
* @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above)
|
||||
*/
|
||||
int bfin_mem_access_type(unsigned long addr, unsigned long size);
|
||||
|
||||
#endif /* _BLACKFIN_UACCESS_H */
|
||||
|
|
|
@ -381,8 +381,9 @@
|
|||
#define __NR_preadv 366
|
||||
#define __NR_pwritev 367
|
||||
#define __NR_rt_tgsigqueueinfo 368
|
||||
#define __NR_perf_counter_open 369
|
||||
|
||||
#define __NR_syscall 369
|
||||
#define __NR_syscall 370
|
||||
#define NR_syscalls __NR_syscall
|
||||
|
||||
/* Old optional stuff no one actually uses */
|
||||
|
|
|
@ -20,7 +20,6 @@ obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
|
|||
CFLAGS_REMOVE_ftrace.o = -pg
|
||||
|
||||
obj-$(CONFIG_IPIPE) += ipipe.o
|
||||
obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o
|
||||
obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
|
||||
obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
|
||||
obj-$(CONFIG_MODULES) += module.o
|
||||
|
|
|
@ -46,13 +46,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
|
|||
|
||||
printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
|
||||
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
|
||||
i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
|
||||
d_cache = CPLB_L1_CHBL;
|
||||
#ifdef CONFIG_BFIN_WT
|
||||
#ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH
|
||||
d_cache |= CPLB_L1_AOW | CPLB_WT;
|
||||
#endif
|
||||
#endif
|
||||
|
@ -91,9 +91,9 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
|
|||
/* Cover L2 memory */
|
||||
#if L2_LENGTH > 0
|
||||
dcplb_tbl[cpu][i_d].addr = L2_START;
|
||||
dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
|
||||
dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
|
||||
icplb_tbl[cpu][i_i].addr = L2_START;
|
||||
icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
|
||||
icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
|
||||
#endif
|
||||
|
||||
first_mask_dcplb = i_d;
|
||||
|
|
|
@ -150,15 +150,19 @@ static noinline int dcplb_miss(unsigned int cpu)
|
|||
nr_dcplb_miss[cpu]++;
|
||||
|
||||
d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
|
||||
if (bfin_addr_dcacheable(addr)) {
|
||||
d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
|
||||
#ifdef CONFIG_BFIN_WT
|
||||
# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
|
||||
d_data |= CPLB_L1_AOW | CPLB_WT;
|
||||
#endif
|
||||
# endif
|
||||
}
|
||||
#endif
|
||||
if (addr >= physical_mem_end) {
|
||||
|
||||
if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
|
||||
addr = L2_START;
|
||||
d_data = L2_DMEMORY;
|
||||
} else if (addr >= physical_mem_end) {
|
||||
if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
|
||||
&& (status & FAULT_USERSUPV)) {
|
||||
addr &= ~0x3fffff;
|
||||
|
@ -235,7 +239,7 @@ static noinline int icplb_miss(unsigned int cpu)
|
|||
|
||||
i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
|
||||
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
|
||||
/*
|
||||
* Normal RAM, and possibly the reserved memory area, are
|
||||
* cacheable.
|
||||
|
@ -245,7 +249,10 @@ static noinline int icplb_miss(unsigned int cpu)
|
|||
i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
|
||||
#endif
|
||||
|
||||
if (addr >= physical_mem_end) {
|
||||
if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
|
||||
addr = L2_START;
|
||||
i_data = L2_IMEMORY;
|
||||
} else if (addr >= physical_mem_end) {
|
||||
if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
|
||||
&& (status & FAULT_USERSUPV)) {
|
||||
addr &= ~(1 * 1024 * 1024 - 1);
|
||||
|
@ -365,13 +372,18 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
|
|||
local_irq_save_hw(flags);
|
||||
current_rwx_mask[cpu] = masks;
|
||||
|
||||
d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
d_data |= CPLB_L1_CHBL;
|
||||
#ifdef CONFIG_BFIN_WT
|
||||
d_data |= CPLB_L1_AOW | CPLB_WT;
|
||||
#endif
|
||||
if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
|
||||
addr = L2_START;
|
||||
d_data = L2_DMEMORY;
|
||||
} else {
|
||||
d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
|
||||
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
|
||||
d_data |= CPLB_L1_CHBL;
|
||||
# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
|
||||
d_data |= CPLB_L1_AOW | CPLB_WT;
|
||||
# endif
|
||||
#endif
|
||||
}
|
||||
|
||||
disable_dcplb();
|
||||
for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
|
||||
|
|
|
@ -52,7 +52,7 @@ EXPORT_SYMBOL(__ipipe_freq_scale);
|
|||
|
||||
atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
|
||||
|
||||
unsigned long __ipipe_irq_lvmask = __all_masked_irq_flags;
|
||||
unsigned long __ipipe_irq_lvmask = bfin_no_irqs;
|
||||
EXPORT_SYMBOL(__ipipe_irq_lvmask);
|
||||
|
||||
static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc)
|
||||
|
@ -342,8 +342,3 @@ void ___ipipe_sync_pipeline(unsigned long syncmask)
|
|||
}
|
||||
|
||||
EXPORT_SYMBOL(show_stack);
|
||||
|
||||
#ifdef CONFIG_IPIPE_TRACE_MCOUNT
|
||||
void notrace _mcount(void);
|
||||
EXPORT_SYMBOL(_mcount);
|
||||
#endif /* CONFIG_IPIPE_TRACE_MCOUNT */
|
||||
|
|
|
@ -38,38 +38,15 @@
|
|||
#include <asm/pda.h>
|
||||
|
||||
static atomic_t irq_err_count;
|
||||
static spinlock_t irq_controller_lock;
|
||||
|
||||
/*
|
||||
* Dummy mask/unmask handler
|
||||
*/
|
||||
void dummy_mask_unmask_irq(unsigned int irq)
|
||||
{
|
||||
}
|
||||
|
||||
void ack_bad_irq(unsigned int irq)
|
||||
{
|
||||
atomic_inc(&irq_err_count);
|
||||
printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
|
||||
}
|
||||
|
||||
static struct irq_chip bad_chip = {
|
||||
.ack = dummy_mask_unmask_irq,
|
||||
.mask = dummy_mask_unmask_irq,
|
||||
.unmask = dummy_mask_unmask_irq,
|
||||
};
|
||||
|
||||
static int bad_stats;
|
||||
static struct irq_desc bad_irq_desc = {
|
||||
.status = IRQ_DISABLED,
|
||||
.chip = &bad_chip,
|
||||
.handle_irq = handle_bad_irq,
|
||||
.depth = 1,
|
||||
.lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock),
|
||||
.kstat_irqs = &bad_stats,
|
||||
#ifdef CONFIG_SMP
|
||||
.affinity = CPU_MASK_ALL
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CPUMASK_OFFSTACK
|
||||
|
@ -77,6 +54,7 @@ static struct irq_desc bad_irq_desc = {
|
|||
#error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK."
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
int show_interrupts(struct seq_file *p, void *v)
|
||||
{
|
||||
int i = *(loff_t *) v, j;
|
||||
|
@ -108,50 +86,29 @@ int show_interrupts(struct seq_file *p, void *v)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* do_IRQ handles all hardware IRQs. Decoded IRQs should not
|
||||
* come via this function. Instead, they should provide their
|
||||
* own 'handler'
|
||||
*/
|
||||
#ifdef CONFIG_DO_IRQ_L1
|
||||
__attribute__((l1_text))
|
||||
#endif
|
||||
asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
|
||||
{
|
||||
struct pt_regs *old_regs;
|
||||
struct irq_desc *desc = irq_desc + irq;
|
||||
#ifndef CONFIG_IPIPE
|
||||
unsigned short pending, other_ints;
|
||||
#endif
|
||||
old_regs = set_irq_regs(regs);
|
||||
|
||||
/*
|
||||
* Some hardware gives randomly wrong interrupts. Rather
|
||||
* than crashing, do something sensible.
|
||||
*/
|
||||
if (irq >= NR_IRQS)
|
||||
desc = &bad_irq_desc;
|
||||
|
||||
irq_enter();
|
||||
#ifdef CONFIG_DEBUG_STACKOVERFLOW
|
||||
static void check_stack_overflow(int irq)
|
||||
{
|
||||
/* Debugging check for stack overflow: is there less than STACK_WARN free? */
|
||||
{
|
||||
long sp;
|
||||
long sp = __get_SP() & (THREAD_SIZE - 1);
|
||||
|
||||
sp = __get_SP() & (THREAD_SIZE-1);
|
||||
|
||||
if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
|
||||
dump_stack();
|
||||
printk(KERN_EMERG "%s: possible stack overflow while handling irq %i "
|
||||
" only %ld bytes free\n",
|
||||
__func__, irq, sp - sizeof(struct thread_info));
|
||||
}
|
||||
if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
|
||||
dump_stack();
|
||||
pr_emerg("irq%i: possible stack overflow only %ld bytes free\n",
|
||||
irq, sp - sizeof(struct thread_info));
|
||||
}
|
||||
}
|
||||
#else
|
||||
static inline void check_stack_overflow(int irq) { }
|
||||
#endif
|
||||
generic_handle_irq(irq);
|
||||
|
||||
#ifndef CONFIG_IPIPE
|
||||
static void maybe_lower_to_irq14(void)
|
||||
{
|
||||
unsigned short pending, other_ints;
|
||||
|
||||
/*
|
||||
* If we're the only interrupt running (ignoring IRQ15 which
|
||||
* is for syscalls), lower our priority to IRQ14 so that
|
||||
|
@ -165,7 +122,38 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
|
|||
other_ints = pending & (pending - 1);
|
||||
if (other_ints == 0)
|
||||
lower_to_irq14();
|
||||
#endif /* !CONFIG_IPIPE */
|
||||
}
|
||||
#else
|
||||
static inline void maybe_lower_to_irq14(void) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* do_IRQ handles all hardware IRQs. Decoded IRQs should not
|
||||
* come via this function. Instead, they should provide their
|
||||
* own 'handler'
|
||||
*/
|
||||
#ifdef CONFIG_DO_IRQ_L1
|
||||
__attribute__((l1_text))
|
||||
#endif
|
||||
asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
|
||||
{
|
||||
struct pt_regs *old_regs = set_irq_regs(regs);
|
||||
|
||||
irq_enter();
|
||||
|
||||
check_stack_overflow(irq);
|
||||
|
||||
/*
|
||||
* Some hardware gives randomly wrong interrupts. Rather
|
||||
* than crashing, do something sensible.
|
||||
*/
|
||||
if (irq >= NR_IRQS)
|
||||
handle_bad_irq(irq, &bad_irq_desc);
|
||||
else
|
||||
generic_handle_irq(irq);
|
||||
|
||||
maybe_lower_to_irq14();
|
||||
|
||||
irq_exit();
|
||||
|
||||
set_irq_regs(old_regs);
|
||||
|
@ -173,14 +161,6 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
|
|||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
int irq;
|
||||
|
||||
spin_lock_init(&irq_controller_lock);
|
||||
for (irq = 0, desc = irq_desc; irq < NR_IRQS; irq++, desc++) {
|
||||
*desc = bad_irq_desc;
|
||||
}
|
||||
|
||||
init_arch_irq();
|
||||
|
||||
#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
|
||||
|
|
|
@ -34,15 +34,6 @@ int gdb_bfin_vector = -1;
|
|||
#error change the definition of slavecpulocks
|
||||
#endif
|
||||
|
||||
#define IN_MEM(addr, size, l1_addr, l1_size) \
|
||||
({ \
|
||||
unsigned long __addr = (unsigned long)(addr); \
|
||||
(l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
|
||||
})
|
||||
#define ASYNC_BANK_SIZE \
|
||||
(ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
|
||||
ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
|
||||
|
||||
void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
|
||||
{
|
||||
gdb_regs[BFIN_R0] = regs->r0;
|
||||
|
@ -463,40 +454,87 @@ static int hex(char ch)
|
|||
|
||||
static int validate_memory_access_address(unsigned long addr, int size)
|
||||
{
|
||||
int cpu = raw_smp_processor_id();
|
||||
|
||||
if (size < 0)
|
||||
if (size < 0 || addr == 0)
|
||||
return -EFAULT;
|
||||
if (addr >= 0x1000 && (addr + size) <= physical_mem_end)
|
||||
return 0;
|
||||
if (addr >= SYSMMR_BASE)
|
||||
return 0;
|
||||
if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
|
||||
return 0;
|
||||
if (cpu == 0) {
|
||||
if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
|
||||
return bfin_mem_access_type(addr, size);
|
||||
}
|
||||
|
||||
static int bfin_probe_kernel_read(char *dst, char *src, int size)
|
||||
{
|
||||
unsigned long lsrc = (unsigned long)src;
|
||||
int mem_type;
|
||||
|
||||
mem_type = validate_memory_access_address(lsrc, size);
|
||||
if (mem_type < 0)
|
||||
return mem_type;
|
||||
|
||||
if (lsrc >= SYSMMR_BASE) {
|
||||
if (size == 2 && lsrc % 2 == 0) {
|
||||
u16 mmr = bfin_read16(src);
|
||||
memcpy(dst, &mmr, sizeof(mmr));
|
||||
return 0;
|
||||
if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH))
|
||||
} else if (size == 4 && lsrc % 4 == 0) {
|
||||
u32 mmr = bfin_read32(src);
|
||||
memcpy(dst, &mmr, sizeof(mmr));
|
||||
return 0;
|
||||
if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
|
||||
return 0;
|
||||
if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
|
||||
return 0;
|
||||
#ifdef CONFIG_SMP
|
||||
} else if (cpu == 1) {
|
||||
if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
|
||||
return 0;
|
||||
if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
|
||||
return 0;
|
||||
if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
|
||||
return 0;
|
||||
if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
} else {
|
||||
switch (mem_type) {
|
||||
case BFIN_MEM_ACCESS_CORE:
|
||||
case BFIN_MEM_ACCESS_CORE_ONLY:
|
||||
return probe_kernel_read(dst, src, size);
|
||||
/* XXX: should support IDMA here with SMP */
|
||||
case BFIN_MEM_ACCESS_DMA:
|
||||
if (dma_memcpy(dst, src, size))
|
||||
return 0;
|
||||
break;
|
||||
case BFIN_MEM_ACCESS_ITEST:
|
||||
if (isram_memcpy(dst, src, size))
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (IN_MEM(addr, size, L2_START, L2_LENGTH))
|
||||
return 0;
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
static int bfin_probe_kernel_write(char *dst, char *src, int size)
|
||||
{
|
||||
unsigned long ldst = (unsigned long)dst;
|
||||
int mem_type;
|
||||
|
||||
mem_type = validate_memory_access_address(ldst, size);
|
||||
if (mem_type < 0)
|
||||
return mem_type;
|
||||
|
||||
if (ldst >= SYSMMR_BASE) {
|
||||
if (size == 2 && ldst % 2 == 0) {
|
||||
u16 mmr;
|
||||
memcpy(&mmr, src, sizeof(mmr));
|
||||
bfin_write16(dst, mmr);
|
||||
return 0;
|
||||
} else if (size == 4 && ldst % 4 == 0) {
|
||||
u32 mmr;
|
||||
memcpy(&mmr, src, sizeof(mmr));
|
||||
bfin_write32(dst, mmr);
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
switch (mem_type) {
|
||||
case BFIN_MEM_ACCESS_CORE:
|
||||
case BFIN_MEM_ACCESS_CORE_ONLY:
|
||||
return probe_kernel_write(dst, src, size);
|
||||
/* XXX: should support IDMA here with SMP */
|
||||
case BFIN_MEM_ACCESS_DMA:
|
||||
if (dma_memcpy(dst, src, size))
|
||||
return 0;
|
||||
break;
|
||||
case BFIN_MEM_ACCESS_ITEST:
|
||||
if (isram_memcpy(dst, src, size))
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return -EFAULT;
|
||||
}
|
||||
|
@ -509,14 +547,6 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
|
|||
{
|
||||
char *tmp;
|
||||
int err;
|
||||
unsigned char *pch;
|
||||
unsigned short mmr16;
|
||||
unsigned long mmr32;
|
||||
int cpu = raw_smp_processor_id();
|
||||
|
||||
err = validate_memory_access_address((unsigned long)mem, count);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* We use the upper half of buf as an intermediate buffer for the
|
||||
|
@ -524,44 +554,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
|
|||
*/
|
||||
tmp = buf + count;
|
||||
|
||||
if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
|
||||
switch (count) {
|
||||
case 2:
|
||||
if ((unsigned int)mem % 2 == 0) {
|
||||
mmr16 = *(unsigned short *)mem;
|
||||
pch = (unsigned char *)&mmr16;
|
||||
*tmp++ = *pch++;
|
||||
*tmp++ = *pch++;
|
||||
tmp -= 2;
|
||||
} else
|
||||
err = -EFAULT;
|
||||
break;
|
||||
case 4:
|
||||
if ((unsigned int)mem % 4 == 0) {
|
||||
mmr32 = *(unsigned long *)mem;
|
||||
pch = (unsigned char *)&mmr32;
|
||||
*tmp++ = *pch++;
|
||||
*tmp++ = *pch++;
|
||||
*tmp++ = *pch++;
|
||||
*tmp++ = *pch++;
|
||||
tmp -= 4;
|
||||
} else
|
||||
err = -EFAULT;
|
||||
break;
|
||||
default:
|
||||
err = -EFAULT;
|
||||
}
|
||||
} else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
|
||||
#ifdef CONFIG_SMP
|
||||
|| (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
|
||||
#endif
|
||||
) {
|
||||
/* access L1 instruction SRAM*/
|
||||
if (dma_memcpy(tmp, mem, count) == NULL)
|
||||
err = -EFAULT;
|
||||
} else
|
||||
err = probe_kernel_read(tmp, mem, count);
|
||||
|
||||
err = bfin_probe_kernel_read(tmp, mem, count);
|
||||
if (!err) {
|
||||
while (count > 0) {
|
||||
buf = pack_hex_byte(buf, *tmp);
|
||||
|
@ -582,13 +575,8 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
|
|||
*/
|
||||
int kgdb_ebin2mem(char *buf, char *mem, int count)
|
||||
{
|
||||
char *tmp_old;
|
||||
char *tmp_new;
|
||||
unsigned short *mmr16;
|
||||
unsigned long *mmr32;
|
||||
int err;
|
||||
char *tmp_old, *tmp_new;
|
||||
int size;
|
||||
int cpu = raw_smp_processor_id();
|
||||
|
||||
tmp_old = tmp_new = buf;
|
||||
|
||||
|
@ -601,41 +589,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
|
|||
tmp_old++;
|
||||
}
|
||||
|
||||
err = validate_memory_access_address((unsigned long)mem, size);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
|
||||
switch (size) {
|
||||
case 2:
|
||||
if ((unsigned int)mem % 2 == 0) {
|
||||
mmr16 = (unsigned short *)buf;
|
||||
*(unsigned short *)mem = *mmr16;
|
||||
} else
|
||||
err = -EFAULT;
|
||||
break;
|
||||
case 4:
|
||||
if ((unsigned int)mem % 4 == 0) {
|
||||
mmr32 = (unsigned long *)buf;
|
||||
*(unsigned long *)mem = *mmr32;
|
||||
} else
|
||||
err = -EFAULT;
|
||||
break;
|
||||
default:
|
||||
err = -EFAULT;
|
||||
}
|
||||
} else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
|
||||
#ifdef CONFIG_SMP
|
||||
|| (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
|
||||
#endif
|
||||
) {
|
||||
/* access L1 instruction SRAM */
|
||||
if (dma_memcpy(mem, buf, size) == NULL)
|
||||
err = -EFAULT;
|
||||
} else
|
||||
err = probe_kernel_write(mem, buf, size);
|
||||
|
||||
return err;
|
||||
return bfin_probe_kernel_write(mem, buf, count);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -645,16 +599,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
|
|||
*/
|
||||
int kgdb_hex2mem(char *buf, char *mem, int count)
|
||||
{
|
||||
char *tmp_raw;
|
||||
char *tmp_hex;
|
||||
unsigned short *mmr16;
|
||||
unsigned long *mmr32;
|
||||
int err;
|
||||
int cpu = raw_smp_processor_id();
|
||||
|
||||
err = validate_memory_access_address((unsigned long)mem, count);
|
||||
if (err)
|
||||
return err;
|
||||
char *tmp_raw, *tmp_hex;
|
||||
|
||||
/*
|
||||
* We use the upper half of buf as an intermediate buffer for the
|
||||
|
@ -669,39 +614,18 @@ int kgdb_hex2mem(char *buf, char *mem, int count)
|
|||
*tmp_raw |= hex(*tmp_hex--) << 4;
|
||||
}
|
||||
|
||||
if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
|
||||
switch (count) {
|
||||
case 2:
|
||||
if ((unsigned int)mem % 2 == 0) {
|
||||
mmr16 = (unsigned short *)tmp_raw;
|
||||
*(unsigned short *)mem = *mmr16;
|
||||
} else
|
||||
err = -EFAULT;
|
||||
break;
|
||||
case 4:
|
||||
if ((unsigned int)mem % 4 == 0) {
|
||||
mmr32 = (unsigned long *)tmp_raw;
|
||||
*(unsigned long *)mem = *mmr32;
|
||||
} else
|
||||
err = -EFAULT;
|
||||
break;
|
||||
default:
|
||||
err = -EFAULT;
|
||||
}
|
||||
} else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
|
||||
#ifdef CONFIG_SMP
|
||||
|| (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
|
||||
#endif
|
||||
) {
|
||||
/* access L1 instruction SRAM */
|
||||
if (dma_memcpy(mem, tmp_raw, count) == NULL)
|
||||
err = -EFAULT;
|
||||
} else
|
||||
err = probe_kernel_write(mem, tmp_raw, count);
|
||||
|
||||
return err;
|
||||
return bfin_probe_kernel_write(mem, tmp_raw, count);
|
||||
}
|
||||
|
||||
#define IN_MEM(addr, size, l1_addr, l1_size) \
|
||||
({ \
|
||||
unsigned long __addr = (unsigned long)(addr); \
|
||||
(l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
|
||||
})
|
||||
#define ASYNC_BANK_SIZE \
|
||||
(ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
|
||||
ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
|
||||
|
||||
int kgdb_validate_break_address(unsigned long addr)
|
||||
{
|
||||
int cpu = raw_smp_processor_id();
|
||||
|
@ -724,46 +648,17 @@ int kgdb_validate_break_address(unsigned long addr)
|
|||
|
||||
int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
|
||||
{
|
||||
int err;
|
||||
int cpu = raw_smp_processor_id();
|
||||
|
||||
if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
|
||||
#ifdef CONFIG_SMP
|
||||
|| (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
|
||||
#endif
|
||||
) {
|
||||
/* access L1 instruction SRAM */
|
||||
if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE)
|
||||
== NULL)
|
||||
return -EFAULT;
|
||||
|
||||
if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr,
|
||||
BREAK_INSTR_SIZE) == NULL)
|
||||
return -EFAULT;
|
||||
|
||||
return 0;
|
||||
} else {
|
||||
err = probe_kernel_read(saved_instr, (char *)addr,
|
||||
BREAK_INSTR_SIZE);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return probe_kernel_write((char *)addr,
|
||||
arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE);
|
||||
}
|
||||
int err = bfin_probe_kernel_read(saved_instr, (char *)addr,
|
||||
BREAK_INSTR_SIZE);
|
||||
if (err)
|
||||
return err;
|
||||
return bfin_probe_kernel_write((char *)addr, arch_kgdb_ops.gdb_bpt_instr,
|
||||
BREAK_INSTR_SIZE);
|
||||
}
|
||||
|
||||
int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
|
||||
{
|
||||
if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) {
|
||||
/* access L1 instruction SRAM */
|
||||
if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
|
||||
return -EFAULT;
|
||||
|
||||
return 0;
|
||||
} else
|
||||
return probe_kernel_write((char *)addr,
|
||||
(char *)bundle, BREAK_INSTR_SIZE);
|
||||
return bfin_probe_kernel_write((char *)addr, bundle, BREAK_INSTR_SIZE);
|
||||
}
|
||||
|
||||
int kgdb_arch_init(void)
|
||||
|
|
|
@ -1,70 +0,0 @@
|
|||
/*
|
||||
* linux/arch/blackfin/mcount.S
|
||||
*
|
||||
* Copyright (C) 2006 Analog Devices Inc.
|
||||
*
|
||||
* 2007/04/12 Save index, length, modify and base registers. --rpm
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
.text
|
||||
|
||||
.align 4 /* just in case */
|
||||
|
||||
ENTRY(__mcount)
|
||||
[--sp] = i0;
|
||||
[--sp] = i1;
|
||||
[--sp] = i2;
|
||||
[--sp] = i3;
|
||||
[--sp] = l0;
|
||||
[--sp] = l1;
|
||||
[--sp] = l2;
|
||||
[--sp] = l3;
|
||||
[--sp] = m0;
|
||||
[--sp] = m1;
|
||||
[--sp] = m2;
|
||||
[--sp] = m3;
|
||||
[--sp] = b0;
|
||||
[--sp] = b1;
|
||||
[--sp] = b2;
|
||||
[--sp] = b3;
|
||||
[--sp] = ( r7:0, p5:0 );
|
||||
[--sp] = ASTAT;
|
||||
|
||||
p1.L = _ipipe_trace_enable;
|
||||
p1.H = _ipipe_trace_enable;
|
||||
r7 = [p1];
|
||||
CC = r7 == 0;
|
||||
if CC jump out;
|
||||
link 0x10;
|
||||
r0 = 0x0;
|
||||
[sp + 0xc] = r0; /* v */
|
||||
r0 = 0x0; /* type: IPIPE_TRACE_FN */
|
||||
r1 = rets;
|
||||
p0 = [fp]; /* p0: Prior FP */
|
||||
r2 = [p0 + 4]; /* r2: Prior RETS */
|
||||
call ___ipipe_trace;
|
||||
unlink;
|
||||
out:
|
||||
ASTAT = [sp++];
|
||||
( r7:0, p5:0 ) = [sp++];
|
||||
b3 = [sp++];
|
||||
b2 = [sp++];
|
||||
b1 = [sp++];
|
||||
b0 = [sp++];
|
||||
m3 = [sp++];
|
||||
m2 = [sp++];
|
||||
m1 = [sp++];
|
||||
m0 = [sp++];
|
||||
l3 = [sp++];
|
||||
l2 = [sp++];
|
||||
l1 = [sp++];
|
||||
l0 = [sp++];
|
||||
i3 = [sp++];
|
||||
i2 = [sp++];
|
||||
i1 = [sp++];
|
||||
i0 = [sp++];
|
||||
rts;
|
||||
ENDPROC(__mcount)
|
|
@ -344,6 +344,87 @@ void finish_atomic_sections (struct pt_regs *regs)
|
|||
}
|
||||
}
|
||||
|
||||
static inline
|
||||
int in_mem(unsigned long addr, unsigned long size,
|
||||
unsigned long start, unsigned long end)
|
||||
{
|
||||
return addr >= start && addr + size <= end;
|
||||
}
|
||||
static inline
|
||||
int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
|
||||
unsigned long const_addr, unsigned long const_size)
|
||||
{
|
||||
return const_size &&
|
||||
in_mem(addr, size, const_addr + off, const_addr + const_size);
|
||||
}
|
||||
static inline
|
||||
int in_mem_const(unsigned long addr, unsigned long size,
|
||||
unsigned long const_addr, unsigned long const_size)
|
||||
{
|
||||
return in_mem_const_off(addr, 0, size, const_addr, const_size);
|
||||
}
|
||||
#define IN_ASYNC(bnum, bctlnum) \
|
||||
({ \
|
||||
(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \
|
||||
bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \
|
||||
BFIN_MEM_ACCESS_CORE; \
|
||||
})
|
||||
|
||||
int bfin_mem_access_type(unsigned long addr, unsigned long size)
|
||||
{
|
||||
int cpu = raw_smp_processor_id();
|
||||
|
||||
/* Check that things do not wrap around */
|
||||
if (addr > ULONG_MAX - size)
|
||||
return -EFAULT;
|
||||
|
||||
if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
|
||||
return BFIN_MEM_ACCESS_CORE;
|
||||
|
||||
if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
|
||||
return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
|
||||
if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
|
||||
return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
|
||||
if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
|
||||
return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
|
||||
if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
|
||||
return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
|
||||
#ifdef COREB_L1_CODE_START
|
||||
if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
|
||||
return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
|
||||
if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
|
||||
return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
|
||||
if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
|
||||
return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
|
||||
if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
|
||||
return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
|
||||
#endif
|
||||
if (in_mem_const(addr, size, L2_START, L2_LENGTH))
|
||||
return BFIN_MEM_ACCESS_CORE;
|
||||
|
||||
if (addr >= SYSMMR_BASE)
|
||||
return BFIN_MEM_ACCESS_CORE_ONLY;
|
||||
|
||||
/* We can't read EBIU banks that aren't enabled or we end up hanging
|
||||
* on the access to the async space.
|
||||
*/
|
||||
if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE))
|
||||
return IN_ASYNC(0, 0);
|
||||
if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE))
|
||||
return IN_ASYNC(1, 0);
|
||||
if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE))
|
||||
return IN_ASYNC(2, 1);
|
||||
if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE))
|
||||
return IN_ASYNC(3, 1);
|
||||
|
||||
if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
|
||||
return BFIN_MEM_ACCESS_CORE;
|
||||
if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
|
||||
return BFIN_MEM_ACCESS_DMA;
|
||||
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ACCESS_CHECK)
|
||||
#ifdef CONFIG_ACCESS_OK_L1
|
||||
__attribute__((l1_text))
|
||||
|
@ -353,51 +434,61 @@ int _access_ok(unsigned long addr, unsigned long size)
|
|||
{
|
||||
if (size == 0)
|
||||
return 1;
|
||||
if (addr > (addr + size))
|
||||
/* Check that things do not wrap around */
|
||||
if (addr > ULONG_MAX - size)
|
||||
return 0;
|
||||
if (segment_eq(get_fs(), KERNEL_DS))
|
||||
return 1;
|
||||
#ifdef CONFIG_MTD_UCLINUX
|
||||
if (addr >= memory_start && (addr + size) <= memory_end)
|
||||
return 1;
|
||||
if (addr >= memory_mtd_end && (addr + size) <= physical_mem_end)
|
||||
if (1)
|
||||
#else
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
if (in_mem(addr, size, memory_start, memory_end))
|
||||
return 1;
|
||||
if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
|
||||
return 1;
|
||||
# ifndef CONFIG_ROMFS_ON_MTD
|
||||
if (0)
|
||||
# endif
|
||||
/* For XIP, allow user space to use pointers within the ROMFS. */
|
||||
if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
|
||||
return 1;
|
||||
} else {
|
||||
if (in_mem(addr, size, memory_start, physical_mem_end))
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
|
||||
return 1;
|
||||
|
||||
#ifdef CONFIG_ROMFS_ON_MTD
|
||||
/* For XIP, allow user space to use pointers within the ROMFS. */
|
||||
if (addr >= memory_mtd_start && (addr + size) <= memory_mtd_end)
|
||||
if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
|
||||
return 1;
|
||||
if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
|
||||
return 1;
|
||||
if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
|
||||
return 1;
|
||||
if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
|
||||
return 1;
|
||||
#ifdef COREB_L1_CODE_START
|
||||
if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
|
||||
return 1;
|
||||
if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
|
||||
return 1;
|
||||
if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
|
||||
return 1;
|
||||
if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
|
||||
return 1;
|
||||
#endif
|
||||
#else
|
||||
if (addr >= memory_start && (addr + size) <= physical_mem_end)
|
||||
if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
|
||||
return 1;
|
||||
#endif
|
||||
if (addr >= (unsigned long)__init_begin &&
|
||||
addr + size <= (unsigned long)__init_end)
|
||||
|
||||
if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
|
||||
return 1;
|
||||
if (addr >= get_l1_scratch_start()
|
||||
&& addr + size <= get_l1_scratch_start() + L1_SCRATCH_LENGTH)
|
||||
if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
|
||||
return 1;
|
||||
#if L1_CODE_LENGTH != 0
|
||||
if (addr >= get_l1_code_start() + (_etext_l1 - _stext_l1)
|
||||
&& addr + size <= get_l1_code_start() + L1_CODE_LENGTH)
|
||||
return 1;
|
||||
#endif
|
||||
#if L1_DATA_A_LENGTH != 0
|
||||
if (addr >= get_l1_data_a_start() + (_ebss_l1 - _sdata_l1)
|
||||
&& addr + size <= get_l1_data_a_start() + L1_DATA_A_LENGTH)
|
||||
return 1;
|
||||
#endif
|
||||
#if L1_DATA_B_LENGTH != 0
|
||||
if (addr >= get_l1_data_b_start() + (_ebss_b_l1 - _sdata_b_l1)
|
||||
&& addr + size <= get_l1_data_b_start() + L1_DATA_B_LENGTH)
|
||||
return 1;
|
||||
#endif
|
||||
#if L2_LENGTH != 0
|
||||
if (addr >= L2_START + (_ebss_l2 - _stext_l2)
|
||||
&& addr + size <= L2_START + L2_LENGTH)
|
||||
return 1;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(_access_ok);
|
||||
|
|
|
@ -117,15 +117,49 @@ void __cpuinit bfin_setup_caches(unsigned int cpu)
|
|||
*/
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
printk(KERN_INFO "Data Cache Enabled for CPU%u"
|
||||
# if defined CONFIG_BFIN_WB
|
||||
" (write-back)"
|
||||
# elif defined CONFIG_BFIN_WT
|
||||
" (write-through)"
|
||||
printk(KERN_INFO " External memory:"
|
||||
# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
|
||||
" cacheable"
|
||||
# else
|
||||
" uncacheable"
|
||||
# endif
|
||||
"\n", cpu);
|
||||
" in instruction cache\n");
|
||||
if (L2_LENGTH)
|
||||
printk(KERN_INFO " L2 SRAM :"
|
||||
# ifdef CONFIG_BFIN_L2_ICACHEABLE
|
||||
" cacheable"
|
||||
# else
|
||||
" uncacheable"
|
||||
# endif
|
||||
" in instruction cache\n");
|
||||
|
||||
#else
|
||||
printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
|
||||
printk(KERN_INFO " External memory:"
|
||||
# if defined CONFIG_BFIN_EXTMEM_WRITEBACK
|
||||
" cacheable (write-back)"
|
||||
# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
|
||||
" cacheable (write-through)"
|
||||
# else
|
||||
" uncacheable"
|
||||
# endif
|
||||
" in data cache\n");
|
||||
if (L2_LENGTH)
|
||||
printk(KERN_INFO " L2 SRAM :"
|
||||
# if defined CONFIG_BFIN_L2_WRITEBACK
|
||||
" cacheable (write-back)"
|
||||
# elif defined CONFIG_BFIN_L2_WRITETHROUGH
|
||||
" cacheable (write-through)"
|
||||
# else
|
||||
" uncacheable"
|
||||
# endif
|
||||
" in data cache\n");
|
||||
#else
|
||||
printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -443,9 +477,11 @@ static __init void parse_cmdline_early(char *cmdline_p)
|
|||
} else if (!memcmp(to, "clkin_hz=", 9)) {
|
||||
to += 9;
|
||||
early_init_clkin_hz(to);
|
||||
#ifdef CONFIG_EARLY_PRINTK
|
||||
} else if (!memcmp(to, "earlyprintk=", 12)) {
|
||||
to += 12;
|
||||
setup_early_printk(to);
|
||||
#endif
|
||||
} else if (!memcmp(to, "memmap=", 7)) {
|
||||
to += 7;
|
||||
parse_memmap(to);
|
||||
|
@ -516,7 +552,7 @@ static __init void memory_setup(void)
|
|||
&& ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
|
||||
mtd_size =
|
||||
PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
|
||||
# if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
|
||||
# if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
|
||||
/* Due to a Hardware Anomaly we need to limit the size of usable
|
||||
* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
|
||||
* 05000263 - Hardware loop corrupted when taking an ICPLB exception
|
||||
|
@ -544,7 +580,7 @@ static __init void memory_setup(void)
|
|||
dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
|
||||
#endif /* CONFIG_MTD_UCLINUX */
|
||||
|
||||
#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
|
||||
#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
|
||||
/* Due to a Hardware Anomaly we need to limit the size of usable
|
||||
* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
|
||||
* 05000263 - Hardware loop corrupted when taking an ICPLB exception
|
||||
|
@ -764,6 +800,11 @@ void __init setup_arch(char **cmdline_p)
|
|||
{
|
||||
unsigned long sclk, cclk;
|
||||
|
||||
/* Check to make sure we are running on the right processor */
|
||||
if (unlikely(CPUID != bfin_cpuid()))
|
||||
printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
|
||||
CPU, bfin_cpuid(), bfin_revid());
|
||||
|
||||
#ifdef CONFIG_DUMMY_CONSOLE
|
||||
conswitchp = &dummy_con;
|
||||
#endif
|
||||
|
@ -778,14 +819,17 @@ void __init setup_arch(char **cmdline_p)
|
|||
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
|
||||
boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
|
||||
|
||||
/* setup memory defaults from the user config */
|
||||
physical_mem_end = 0;
|
||||
_ramend = get_mem_size() * 1024 * 1024;
|
||||
|
||||
memset(&bfin_memmap, 0, sizeof(bfin_memmap));
|
||||
|
||||
/* If the user does not specify things on the command line, use
|
||||
* what the bootloader set things up as
|
||||
*/
|
||||
physical_mem_end = 0;
|
||||
parse_cmdline_early(&command_line[0]);
|
||||
|
||||
if (_ramend == 0)
|
||||
_ramend = get_mem_size() * 1024 * 1024;
|
||||
|
||||
if (physical_mem_end == 0)
|
||||
physical_mem_end = _ramend;
|
||||
|
||||
|
@ -837,7 +881,8 @@ void __init setup_arch(char **cmdline_p)
|
|||
defined(CONFIG_BF538) || defined(CONFIG_BF539)
|
||||
_bfin_swrst = bfin_read_SWRST();
|
||||
#else
|
||||
_bfin_swrst = bfin_read_SYSCR();
|
||||
/* Clear boot mode field */
|
||||
_bfin_swrst = bfin_read_SYSCR() & ~0xf;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
|
||||
|
@ -875,10 +920,7 @@ void __init setup_arch(char **cmdline_p)
|
|||
else
|
||||
printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
|
||||
|
||||
if (unlikely(CPUID != bfin_cpuid()))
|
||||
printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
|
||||
CPU, bfin_cpuid(), bfin_revid());
|
||||
else {
|
||||
if (likely(CPUID == bfin_cpuid())) {
|
||||
if (bfin_revid() != bfin_compiled_revid()) {
|
||||
if (bfin_compiled_revid() == -1)
|
||||
printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
|
||||
|
@ -1157,16 +1199,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
icache_size = 0;
|
||||
|
||||
seq_printf(m, "cache size\t: %d KB(L1 icache) "
|
||||
"%d KB(L1 dcache%s) %d KB(L2 cache)\n",
|
||||
icache_size, dcache_size,
|
||||
#if defined CONFIG_BFIN_WB
|
||||
"-wb"
|
||||
#elif defined CONFIG_BFIN_WT
|
||||
"-wt"
|
||||
#endif
|
||||
"", 0);
|
||||
|
||||
"%d KB(L1 dcache) %d KB(L2 cache)\n",
|
||||
icache_size, dcache_size, 0);
|
||||
seq_printf(m, "%s\n", cache);
|
||||
seq_printf(m, "external memory\t: "
|
||||
#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
|
||||
"cacheable"
|
||||
#else
|
||||
"uncacheable"
|
||||
#endif
|
||||
" in instruction cache\n");
|
||||
seq_printf(m, "external memory\t: "
|
||||
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
|
||||
"cacheable (write-back)"
|
||||
#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
|
||||
"cacheable (write-through)"
|
||||
#else
|
||||
"uncacheable"
|
||||
#endif
|
||||
" in data cache\n");
|
||||
|
||||
if (icache_size)
|
||||
seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
|
||||
|
@ -1239,8 +1290,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
if (cpu_num != num_possible_cpus() - 1)
|
||||
return 0;
|
||||
|
||||
if (L2_LENGTH)
|
||||
if (L2_LENGTH) {
|
||||
seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
|
||||
seq_printf(m, "L2 SRAM\t\t: "
|
||||
#if defined(CONFIG_BFIN_L2_ICACHEABLE)
|
||||
"cacheable"
|
||||
#else
|
||||
"uncacheable"
|
||||
#endif
|
||||
" in instruction cache\n");
|
||||
seq_printf(m, "L2 SRAM\t\t: "
|
||||
#if defined(CONFIG_BFIN_L2_WRITEBACK)
|
||||
"cacheable (write-back)"
|
||||
#elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
|
||||
"cacheable (write-through)"
|
||||
#else
|
||||
"uncacheable"
|
||||
#endif
|
||||
" in data cache\n");
|
||||
}
|
||||
seq_printf(m, "board name\t: %s\n", bfin_board_name);
|
||||
seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
|
||||
physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
#include <asm/traps.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cplb.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irq_handler.h>
|
||||
#include <linux/irq.h>
|
||||
|
@ -636,57 +637,30 @@ asmlinkage void trap_c(struct pt_regs *fp)
|
|||
*/
|
||||
static bool get_instruction(unsigned short *val, unsigned short *address)
|
||||
{
|
||||
|
||||
unsigned long addr;
|
||||
|
||||
addr = (unsigned long)address;
|
||||
unsigned long addr = (unsigned long)address;
|
||||
|
||||
/* Check for odd addresses */
|
||||
if (addr & 0x1)
|
||||
return false;
|
||||
|
||||
/* Check that things do not wrap around */
|
||||
if (addr > (addr + 2))
|
||||
/* MMR region will never have instructions */
|
||||
if (addr >= SYSMMR_BASE)
|
||||
return false;
|
||||
|
||||
/*
|
||||
* Since we are in exception context, we need to do a little address checking
|
||||
* We need to make sure we are only accessing valid memory, and
|
||||
* we don't read something in the async space that can hang forever
|
||||
*/
|
||||
if ((addr >= FIXED_CODE_START && (addr + 2) <= physical_mem_end) ||
|
||||
#if L2_LENGTH != 0
|
||||
(addr >= L2_START && (addr + 2) <= (L2_START + L2_LENGTH)) ||
|
||||
#endif
|
||||
(addr >= BOOT_ROM_START && (addr + 2) <= (BOOT_ROM_START + BOOT_ROM_LENGTH)) ||
|
||||
#if L1_DATA_A_LENGTH != 0
|
||||
(addr >= L1_DATA_A_START && (addr + 2) <= (L1_DATA_A_START + L1_DATA_A_LENGTH)) ||
|
||||
#endif
|
||||
#if L1_DATA_B_LENGTH != 0
|
||||
(addr >= L1_DATA_B_START && (addr + 2) <= (L1_DATA_B_START + L1_DATA_B_LENGTH)) ||
|
||||
#endif
|
||||
(addr >= L1_SCRATCH_START && (addr + 2) <= (L1_SCRATCH_START + L1_SCRATCH_LENGTH)) ||
|
||||
(!(bfin_read_EBIU_AMBCTL0() & B0RDYEN) &&
|
||||
addr >= ASYNC_BANK0_BASE && (addr + 2) <= (ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)) ||
|
||||
(!(bfin_read_EBIU_AMBCTL0() & B1RDYEN) &&
|
||||
addr >= ASYNC_BANK1_BASE && (addr + 2) <= (ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)) ||
|
||||
(!(bfin_read_EBIU_AMBCTL1() & B2RDYEN) &&
|
||||
addr >= ASYNC_BANK2_BASE && (addr + 2) <= (ASYNC_BANK2_BASE + ASYNC_BANK1_SIZE)) ||
|
||||
(!(bfin_read_EBIU_AMBCTL1() & B3RDYEN) &&
|
||||
addr >= ASYNC_BANK3_BASE && (addr + 2) <= (ASYNC_BANK3_BASE + ASYNC_BANK1_SIZE))) {
|
||||
*val = *address;
|
||||
return true;
|
||||
switch (bfin_mem_access_type(addr, 2)) {
|
||||
case BFIN_MEM_ACCESS_CORE:
|
||||
case BFIN_MEM_ACCESS_CORE_ONLY:
|
||||
*val = *address;
|
||||
return true;
|
||||
case BFIN_MEM_ACCESS_DMA:
|
||||
dma_memcpy(val, address, 2);
|
||||
return true;
|
||||
case BFIN_MEM_ACCESS_ITEST:
|
||||
isram_memcpy(val, address, 2);
|
||||
return true;
|
||||
default: /* invalid access */
|
||||
return false;
|
||||
}
|
||||
|
||||
#if L1_CODE_LENGTH != 0
|
||||
if (addr >= L1_CODE_START && (addr + 2) <= (L1_CODE_START + L1_CODE_LENGTH)) {
|
||||
isram_memcpy(val, address, 2);
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -119,13 +119,19 @@ static struct platform_device bfin_mac_device = {
|
|||
};
|
||||
|
||||
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
|
||||
static struct dsa_platform_data ksz8893m_switch_data = {
|
||||
static struct dsa_chip_data ksz8893m_switch_chip_data = {
|
||||
.mii_bus = &bfin_mii_bus.dev,
|
||||
.port_names = {
|
||||
NULL,
|
||||
"eth%d",
|
||||
"eth%d",
|
||||
"cpu",
|
||||
},
|
||||
};
|
||||
static struct dsa_platform_data ksz8893m_switch_data = {
|
||||
.nr_chips = 1,
|
||||
.netdev = &bfin_mac_device.dev,
|
||||
.port_names[0] = NULL,
|
||||
.port_names[1] = "eth%d",
|
||||
.port_names[2] = "eth%d",
|
||||
.port_names[3] = "cpu",
|
||||
.chip = &ksz8893m_switch_chip_data,
|
||||
};
|
||||
|
||||
static struct platform_device ksz8893m_switch_device = {
|
||||
|
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/* This file should be up to date with:
|
||||
* - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
|
||||
* - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
|
||||
|
@ -18,7 +18,7 @@
|
|||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
|
@ -45,29 +45,31 @@
|
|||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (1)
|
||||
#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
|
||||
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
|
||||
#define ANOMALY_05000431 (1)
|
||||
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
|
||||
#define ANOMALY_05000435 (1)
|
||||
#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
|
||||
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
|
||||
#define ANOMALY_05000438 (1)
|
||||
#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
|
||||
/* Preboot Cannot be Used to Alter the PLL_DIV Register */
|
||||
#define ANOMALY_05000439 (1)
|
||||
#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
|
||||
#define ANOMALY_05000440 (1)
|
||||
#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* Incorrect L1 Instruction Bank B Memory Map Location */
|
||||
#define ANOMALY_05000444 (1)
|
||||
#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
|
||||
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
|
||||
#define ANOMALY_05000452 (1)
|
||||
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
|
||||
/* PWM_TRIPB Signal Not Available on PG10 */
|
||||
#define ANOMALY_05000453 (1)
|
||||
#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
|
||||
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
|
||||
#define ANOMALY_05000455 (1)
|
||||
/* False Hardware Error when RETI points to invalid memory */
|
||||
#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
|
||||
#define ANOMALY_05000462 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
|
@ -78,24 +80,30 @@
|
|||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000179 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000244 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000250 (0)
|
||||
#define ANOMALY_05000257 (0)
|
||||
#define ANOMALY_05000261 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000281 (0)
|
||||
#define ANOMALY_05000283 (0)
|
||||
#define ANOMALY_05000285 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000301 (0)
|
||||
|
@ -103,10 +111,13 @@
|
|||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000312 (0)
|
||||
#define ANOMALY_05000315 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (0)
|
||||
#define ANOMALY_05000357 (0)
|
||||
#define ANOMALY_05000362 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000371 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000386 (0)
|
||||
#define ANOMALY_05000389 (0)
|
||||
|
@ -117,5 +128,7 @@
|
|||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000456 (0)
|
||||
#define ANOMALY_05000450 (0)
|
||||
#define ANOMALY_05000465 (0)
|
||||
#define ANOMALY_05000467 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
#define _MACH_BLACKFIN_H_
|
||||
|
||||
#include "bf518.h"
|
||||
#include "mem_map.h"
|
||||
#include "defBF512.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
|
|
|
@ -1,38 +1,16 @@
|
|||
/*
|
||||
* file: include/asm-blackfin/mach-bf518/mem_map.h
|
||||
* based on: include/asm-blackfin/mach-bf527/mem_map.h
|
||||
* author: Bryan Wu <cooloney@kernel.org>
|
||||
* BF51x memory map
|
||||
*
|
||||
* created:
|
||||
* description:
|
||||
* Memory MAP Common header file for blackfin BF518/6/4/2 of processors.
|
||||
* rev:
|
||||
*
|
||||
* modified:
|
||||
*
|
||||
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* this program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the gnu general public license as published by
|
||||
* the free software foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* this program is distributed in the hope that it will be useful,
|
||||
* but without any warranty; without even the implied warranty of
|
||||
* merchantability or fitness for a particular purpose. see the
|
||||
* gnu general public license for more details.
|
||||
*
|
||||
* you should have received a copy of the gnu general public license
|
||||
* along with this program; see the file copying.
|
||||
* if not, write to the free software foundation,
|
||||
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_518_H_
|
||||
#define _MEM_MAP_518_H_
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||
|
@ -89,20 +67,4 @@
|
|||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE */
|
||||
|
||||
/* Level 2 Memory - none */
|
||||
|
||||
#define L2_START 0
|
||||
#define L2_LENGTH 0
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
#define L1_SCRATCH_START 0xFFB00000
|
||||
#define L1_SCRATCH_LENGTH 0x1000
|
||||
|
||||
#define GET_PDA_SAFE(preg) \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda;
|
||||
|
||||
#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
||||
|
||||
#endif /* _MEM_MAP_518_H_ */
|
||||
#endif
|
||||
|
|
|
@ -78,7 +78,6 @@ static struct resource bfin_isp1760_resources[] = {
|
|||
|
||||
static struct isp1760_platform_data isp1760_priv = {
|
||||
.is_isp1761 = 0,
|
||||
.port1_disable = 0,
|
||||
.bus_width_16 = 1,
|
||||
.port1_otg = 0,
|
||||
.analog_oc = 0,
|
||||
|
|
|
@ -237,10 +237,10 @@ static struct flash_platform_data bfin_spi_flash_data = {
|
|||
.name = "m25p80",
|
||||
.parts = bfin_spi_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
|
||||
.type = "m25p16",
|
||||
.type = "sst25wf040",
|
||||
};
|
||||
|
||||
/* SPI flash chip (m25p64) */
|
||||
/* SPI flash chip (sst25wf040) */
|
||||
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||
.bits_per_word = 8,
|
||||
|
|
|
@ -77,7 +77,6 @@ static struct resource bfin_isp1760_resources[] = {
|
|||
|
||||
static struct isp1760_platform_data isp1760_priv = {
|
||||
.is_isp1761 = 0,
|
||||
.port1_disable = 0,
|
||||
.bus_width_16 = 1,
|
||||
.port1_otg = 0,
|
||||
.analog_oc = 0,
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
|
||||
#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
|
||||
|
||||
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
|
||||
|
@ -184,8 +184,12 @@
|
|||
#define ANOMALY_05000456 (1)
|
||||
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
|
||||
#define ANOMALY_05000457 (1)
|
||||
/* False Hardware Error when RETI points to invalid memory */
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* USB Rx DMA hang */
|
||||
#define ANOMALY_05000465 (1)
|
||||
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
|
||||
#define ANOMALY_05000467 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
|
@ -195,24 +199,30 @@
|
|||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000179 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000244 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000250 (0)
|
||||
#define ANOMALY_05000257 (0)
|
||||
#define ANOMALY_05000261 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000281 (0)
|
||||
#define ANOMALY_05000283 (0)
|
||||
#define ANOMALY_05000285 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000301 (0)
|
||||
|
@ -220,6 +230,7 @@
|
|||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000312 (0)
|
||||
#define ANOMALY_05000315 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000362 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
#define _MACH_BLACKFIN_H_
|
||||
|
||||
#include "bf527.h"
|
||||
#include "mem_map.h"
|
||||
#include "defBF522.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
|
|
|
@ -1,38 +1,16 @@
|
|||
/*
|
||||
* file: include/asm-blackfin/mach-bf527/mem_map.h
|
||||
* based on: include/asm-blackfin/mach-bf537/mem_map.h
|
||||
* author: Michael Hennerich (michael.hennerich@analog.com)
|
||||
* BF52x memory map
|
||||
*
|
||||
* created:
|
||||
* description:
|
||||
* Memory MAP Common header file for blackfin BF527/5/2 of processors.
|
||||
* rev:
|
||||
*
|
||||
* modified:
|
||||
*
|
||||
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* this program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the gnu general public license as published by
|
||||
* the free software foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* this program is distributed in the hope that it will be useful,
|
||||
* but without any warranty; without even the implied warranty of
|
||||
* merchantability or fitness for a particular purpose. see the
|
||||
* gnu general public license for more details.
|
||||
*
|
||||
* you should have received a copy of the gnu general public license
|
||||
* along with this program; see the file copying.
|
||||
* if not, write to the free software foundation,
|
||||
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_527_H_
|
||||
#define _MEM_MAP_527_H_
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||
|
@ -89,20 +67,4 @@
|
|||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE */
|
||||
|
||||
/* Level 2 Memory - none */
|
||||
|
||||
#define L2_START 0
|
||||
#define L2_LENGTH 0
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
#define L1_SCRATCH_START 0xFFB00000
|
||||
#define L1_SCRATCH_LENGTH 0x1000
|
||||
|
||||
#define GET_PDA_SAFE(preg) \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda;
|
||||
|
||||
#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
||||
|
||||
#endif /* _MEM_MAP_527_H_ */
|
||||
#endif
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/plat-ram.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/flash.h>
|
||||
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
|
||||
|
@ -86,6 +87,101 @@ static struct platform_device smc91x_device = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE)
|
||||
static const char *map_probes[] = {
|
||||
"stm_flash",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct platdata_mtd_ram stm_pri_data_a = {
|
||||
.mapname = "Flash A Primary",
|
||||
.map_probes = map_probes,
|
||||
.bankwidth = 2,
|
||||
};
|
||||
|
||||
static struct resource stm_pri_resource_a = {
|
||||
.start = 0x20000000,
|
||||
.end = 0x200fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device stm_pri_device_a = {
|
||||
.name = "mtd-ram",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &stm_pri_data_a,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &stm_pri_resource_a,
|
||||
};
|
||||
|
||||
static struct platdata_mtd_ram stm_pri_data_b = {
|
||||
.mapname = "Flash B Primary",
|
||||
.map_probes = map_probes,
|
||||
.bankwidth = 2,
|
||||
};
|
||||
|
||||
static struct resource stm_pri_resource_b = {
|
||||
.start = 0x20100000,
|
||||
.end = 0x201fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device stm_pri_device_b = {
|
||||
.name = "mtd-ram",
|
||||
.id = 4,
|
||||
.dev = {
|
||||
.platform_data = &stm_pri_data_b,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &stm_pri_resource_b,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
|
||||
static struct platdata_mtd_ram sram_data_a = {
|
||||
.mapname = "Flash A SRAM",
|
||||
.bankwidth = 2,
|
||||
};
|
||||
|
||||
static struct resource sram_resource_a = {
|
||||
.start = 0x20240000,
|
||||
.end = 0x2024ffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device sram_device_a = {
|
||||
.name = "mtd-ram",
|
||||
.id = 8,
|
||||
.dev = {
|
||||
.platform_data = &sram_data_a,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &sram_resource_a,
|
||||
};
|
||||
|
||||
static struct platdata_mtd_ram sram_data_b = {
|
||||
.mapname = "Flash B SRAM",
|
||||
.bankwidth = 2,
|
||||
};
|
||||
|
||||
static struct resource sram_resource_b = {
|
||||
.start = 0x202c0000,
|
||||
.end = 0x202cffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device sram_device_b = {
|
||||
.name = "mtd-ram",
|
||||
.id = 9,
|
||||
.dev = {
|
||||
.platform_data = &sram_data_b,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &sram_resource_b,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
|
||||
static struct mtd_partition bfin_spi_flash_partitions[] = {
|
||||
{
|
||||
|
@ -357,6 +453,16 @@ static struct platform_device *ezkit_devices[] __initdata = {
|
|||
|
||||
&bfin_dpmc,
|
||||
|
||||
#if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE)
|
||||
&stm_pri_device_a,
|
||||
&stm_pri_device_b,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
|
||||
&sram_device_a,
|
||||
&sram_device_b,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
|
||||
&smc91x_device,
|
||||
#endif
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
# define ANOMALY_BF533 0
|
||||
#endif
|
||||
|
||||
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
|
||||
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
|
||||
|
@ -46,7 +46,7 @@
|
|||
#define ANOMALY_05000122 (1)
|
||||
/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
|
||||
#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
#define ANOMALY_05000166 (1)
|
||||
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
|
||||
#define ANOMALY_05000167 (1)
|
||||
|
@ -56,13 +56,13 @@
|
|||
#define ANOMALY_05000180 (1)
|
||||
/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
|
||||
#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
|
||||
/* False Protection Exceptions */
|
||||
/* False Protection Exceptions when Speculative Fetch Is Cancelled */
|
||||
#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
|
||||
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
|
||||
#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
|
||||
/* Restarting SPORT in Specific Modes May Cause Data Corruption */
|
||||
#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
|
||||
/* Failing MMR Accesses When Stalled by Preceding Memory Read */
|
||||
/* Failing MMR Accesses when Preceding Memory Read Stalls */
|
||||
#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
|
||||
/* Current DMA Address Shows Wrong Value During Carry Fix */
|
||||
#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
|
||||
|
@ -74,7 +74,7 @@
|
|||
#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
|
||||
/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
|
||||
#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
|
||||
/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
|
||||
/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
|
||||
#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
|
||||
/* Recovery from "Brown-Out" Condition */
|
||||
#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
|
||||
|
@ -106,7 +106,7 @@
|
|||
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* Data CPLBs Should Prevent Spurious Hardware Errors */
|
||||
/* Data CPLBs Should Prevent False Hardware Errors */
|
||||
#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
|
||||
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
|
||||
#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
|
||||
|
@ -148,21 +148,21 @@
|
|||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
|
||||
/* False Hardware Error Exception When ISR Context Is Not Restored */
|
||||
/* False Hardware Error Exception when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
|
||||
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
|
||||
#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
|
||||
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
|
||||
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
|
||||
#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
|
||||
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
|
||||
#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
|
||||
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
|
||||
#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
|
||||
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
|
||||
/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
|
||||
#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
|
||||
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
|
||||
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
|
||||
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
|
||||
/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
|
||||
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
|
||||
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
|
||||
#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
|
||||
|
@ -170,11 +170,11 @@
|
|||
#define ANOMALY_05000310 (1)
|
||||
/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
|
||||
#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
|
||||
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
|
||||
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
|
||||
#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
|
||||
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
|
||||
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
|
||||
#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
|
||||
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
|
||||
#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
|
||||
|
@ -200,7 +200,7 @@
|
|||
#define ANOMALY_05000426 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* False Hardware Error when RETI points to invalid memory */
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
|
||||
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
|
@ -215,17 +215,17 @@
|
|||
#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
|
||||
/* Writing FIO_DIR can corrupt a programmable flag's data */
|
||||
#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
|
||||
/* Timer Auto-Baud Mode requires the UART clock to be enabled */
|
||||
/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
|
||||
#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
|
||||
/* Internal Clocking Modes on SPORT0 not supported */
|
||||
#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
|
||||
/* Internal voltage regulator does not wake up from an RTC wakeup */
|
||||
#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
|
||||
/* The IFLUSH instruction must be preceded by a CSYNC instruction */
|
||||
/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
|
||||
#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
|
||||
/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */
|
||||
/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
|
||||
#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
|
||||
/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */
|
||||
/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
|
||||
#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
|
||||
/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
|
||||
#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
|
||||
|
@ -235,45 +235,45 @@
|
|||
#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
|
||||
/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
|
||||
#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
|
||||
/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
|
||||
/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
|
||||
#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
|
||||
/* Incorrect value written to the cycle counters */
|
||||
/* Incorrect Value Written to the Cycle Counters */
|
||||
#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
|
||||
/* Stores to L1 Data memory incorrect when a specific sequence is followed */
|
||||
/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
|
||||
#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
|
||||
/* Programmable Flag (PF3) functionality not supported in all PPI modes */
|
||||
#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
|
||||
/* Data store can be lost when targeting a cache line fill */
|
||||
#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
|
||||
/* Reserved bits in SYSCFG register not set at power on */
|
||||
/* Reserved Bits in SYSCFG Register Not Set at Power-On */
|
||||
#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
|
||||
/* Infinite Core Stall */
|
||||
#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
|
||||
/* PPI_FSx may glitch when generated by the on chip Timers */
|
||||
/* PPI_FSx may glitch when generated by the on chip Timers. */
|
||||
#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
|
||||
/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
|
||||
/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
|
||||
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
|
||||
/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
|
||||
#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
|
||||
/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
|
||||
#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
|
||||
/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
|
||||
/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
|
||||
#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
|
||||
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
|
||||
#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
|
||||
/* Erroneous exception when enabling cache */
|
||||
/* Erroneous Exception when Enabling Cache */
|
||||
#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
|
||||
/* SPI clock polarity and phase bits incorrect during booting */
|
||||
#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
|
||||
/* DMEM_CONTROL is not set on Reset */
|
||||
/* DMEM_CONTROL<12> Is Not Set on Reset */
|
||||
#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
|
||||
/* SPI boot will not complete if there is a zero fill block in the loader file */
|
||||
#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
|
||||
/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */
|
||||
/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
|
||||
#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
|
||||
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
|
||||
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
|
||||
/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
|
||||
/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
|
||||
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
|
||||
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
|
||||
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
|
||||
|
@ -287,7 +287,7 @@
|
|||
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
|
||||
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
|
||||
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
|
||||
/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
|
||||
/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
|
||||
#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
|
||||
/* Frame Delay in SPORT Multichannel Mode */
|
||||
#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
|
||||
|
@ -295,13 +295,13 @@
|
|||
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
|
||||
/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
|
||||
#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
|
||||
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
|
||||
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
|
||||
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT transmit data is not gated by external frame sync in certain conditions */
|
||||
/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
|
||||
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
|
||||
/* SDRAM auto-refresh and subsequent Power Ups */
|
||||
/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
|
||||
#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
|
||||
/* DATA CPLB page miss can result in lost write-through cache data writes */
|
||||
/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
|
||||
#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
|
||||
/* DMA vs Core accesses to external memory */
|
||||
#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
|
||||
|
@ -309,15 +309,15 @@
|
|||
#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
|
||||
/* Overlapping Sequencer and Memory Stalls */
|
||||
#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
|
||||
/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
|
||||
/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
|
||||
#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
|
||||
/* Disabling the PPI resets the PPI configuration registers */
|
||||
/* Disabling the PPI Resets the PPI Configuration Registers */
|
||||
#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
|
||||
/* PPI TX Mode with 2 External Frame Syncs */
|
||||
/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
|
||||
#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
|
||||
/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
|
||||
#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
|
||||
/* In PPI Transmit Modes with External Frame Syncs POLC */
|
||||
/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
|
||||
#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
|
||||
/* Internal Voltage Regulator may not start up */
|
||||
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
|
||||
|
@ -326,6 +326,7 @@
|
|||
#define ANOMALY_05000120 (0)
|
||||
#define ANOMALY_05000149 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
|
@ -345,5 +346,7 @@
|
|||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000456 (0)
|
||||
#define ANOMALY_05000450 (0)
|
||||
#define ANOMALY_05000465 (0)
|
||||
#define ANOMALY_05000467 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
#define BF533_FAMILY
|
||||
|
||||
#include "bf533.h"
|
||||
#include "mem_map.h"
|
||||
#include "defBF532.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
|
|
|
@ -1,38 +1,16 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf533/mem_map.h
|
||||
* Based on:
|
||||
* Author:
|
||||
* BF533 memory map
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_533_H_
|
||||
#define _MEM_MAP_533_H_
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||
|
@ -158,20 +136,4 @@
|
|||
|
||||
#endif
|
||||
|
||||
/* Level 2 Memory - none */
|
||||
|
||||
#define L2_START 0
|
||||
#define L2_LENGTH 0
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
#define L1_SCRATCH_START 0xFFB00000
|
||||
#define L1_SCRATCH_LENGTH 0x1000
|
||||
|
||||
#define GET_PDA_SAFE(preg) \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda;
|
||||
|
||||
#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
||||
|
||||
#endif /* _MEM_MAP_533_H_ */
|
||||
#endif
|
||||
|
|
|
@ -79,7 +79,6 @@ static struct resource bfin_isp1760_resources[] = {
|
|||
|
||||
static struct isp1760_platform_data isp1760_priv = {
|
||||
.is_isp1761 = 0,
|
||||
.port1_disable = 0,
|
||||
.bus_width_16 = 1,
|
||||
.port1_otg = 0,
|
||||
.analog_oc = 0,
|
||||
|
|
|
@ -34,13 +34,13 @@
|
|||
# define ANOMALY_BF537 0
|
||||
#endif
|
||||
|
||||
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
|
||||
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
|
||||
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
|
||||
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
|
||||
#define ANOMALY_05000180 (1)
|
||||
|
@ -50,11 +50,11 @@
|
|||
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
|
||||
/* Buffered CLKIN Output Is Disabled by Default */
|
||||
#define ANOMALY_05000247 (1)
|
||||
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
|
||||
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC Tx DMA error after an early frame abort */
|
||||
/* EMAC TX DMA Error After an Early Frame Abort */
|
||||
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
|
||||
/* Maximum External Clock Speed for Timers */
|
||||
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
|
||||
|
@ -62,7 +62,7 @@
|
|||
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
|
||||
/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
|
||||
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC MDIO input latched on wrong MDC edge */
|
||||
/* EMAC MDIO Input Latched on Wrong MDC Edge */
|
||||
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
|
||||
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
|
||||
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
|
||||
|
@ -80,7 +80,7 @@
|
|||
#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
|
||||
/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
|
||||
#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
|
||||
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
|
||||
#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
|
||||
|
@ -92,15 +92,15 @@
|
|||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
|
||||
/* SPI Master boot mode does not work well with Atmel Data flash devices */
|
||||
/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
|
||||
#define ANOMALY_05000280 (1)
|
||||
/* False Hardware Error Exception When ISR Context Is Not Restored */
|
||||
/* False Hardware Error Exception when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
|
||||
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
|
||||
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
|
||||
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
|
||||
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
|
||||
#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
|
||||
/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
|
||||
/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
|
||||
#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
|
||||
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
|
||||
#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
|
||||
|
@ -112,25 +112,25 @@
|
|||
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
|
||||
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
|
||||
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
|
||||
/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
|
||||
/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
|
||||
#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (1)
|
||||
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
|
||||
#define ANOMALY_05000313 (1)
|
||||
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
|
||||
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
|
||||
#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC RMII mode: collisions occur in Full Duplex mode */
|
||||
/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
|
||||
#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
|
||||
/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
|
||||
#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
|
||||
/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
|
||||
/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
|
||||
#define ANOMALY_05000322 (1)
|
||||
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
|
||||
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
|
||||
/* New Feature: UART Remains Enabled after UART Boot */
|
||||
/* UART Gets Disabled after UART Boot */
|
||||
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (1)
|
||||
|
@ -154,7 +154,7 @@
|
|||
#define ANOMALY_05000426 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* False Hardware Error when RETI points to invalid memory */
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
|
@ -165,14 +165,17 @@
|
|||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000179 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
|
@ -195,5 +198,7 @@
|
|||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000456 (0)
|
||||
#define ANOMALY_05000450 (0)
|
||||
#define ANOMALY_05000465 (0)
|
||||
#define ANOMALY_05000467 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
#define BF537_FAMILY
|
||||
|
||||
#include "bf537.h"
|
||||
#include "mem_map.h"
|
||||
#include "defBF534.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
|
|
|
@ -1,38 +1,16 @@
|
|||
/*
|
||||
* file: include/asm-blackfin/mach-bf537/mem_map.h
|
||||
* based on:
|
||||
* author:
|
||||
* BF537 memory map
|
||||
*
|
||||
* created:
|
||||
* description:
|
||||
* Memory MAP Common header file for blackfin BF537/6/4 of processors.
|
||||
* rev:
|
||||
*
|
||||
* modified:
|
||||
*
|
||||
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* this program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the gnu general public license as published by
|
||||
* the free software foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* this program is distributed in the hope that it will be useful,
|
||||
* but without any warranty; without even the implied warranty of
|
||||
* merchantability or fitness for a particular purpose. see the
|
||||
* gnu general public license for more details.
|
||||
*
|
||||
* you should have received a copy of the gnu general public license
|
||||
* along with this program; see the file copying.
|
||||
* if not, write to the free software foundation,
|
||||
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_537_H_
|
||||
#define _MEM_MAP_537_H_
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||
|
@ -166,20 +144,4 @@
|
|||
|
||||
#endif
|
||||
|
||||
/* Level 2 Memory - none */
|
||||
|
||||
#define L2_START 0
|
||||
#define L2_LENGTH 0
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
#define L1_SCRATCH_START 0xFFB00000
|
||||
#define L1_SCRATCH_LENGTH 0x1000
|
||||
|
||||
#define GET_PDA_SAFE(preg) \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda;
|
||||
|
||||
#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
||||
|
||||
#endif /* _MEM_MAP_537_H_ */
|
||||
#endif
|
||||
|
|
|
@ -30,13 +30,13 @@
|
|||
# define ANOMALY_BF539 0
|
||||
#endif
|
||||
|
||||
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
#define ANOMALY_05000166 (1)
|
||||
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
|
||||
#define ANOMALY_05000179 (1)
|
||||
|
@ -70,11 +70,11 @@
|
|||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
|
||||
/* False Hardware Error Exception When ISR Context Is Not Restored */
|
||||
/* False Hardware Error Exception when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
|
||||
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
|
||||
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
|
||||
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
|
||||
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
|
||||
#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
|
||||
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
|
||||
#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
|
||||
|
@ -92,11 +92,11 @@
|
|||
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
|
||||
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
|
||||
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
|
||||
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
|
||||
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
|
||||
/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
|
||||
#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
|
||||
|
@ -110,7 +110,7 @@
|
|||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
|
||||
/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
|
||||
#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
|
||||
/* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */
|
||||
/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
|
||||
#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ < 4)
|
||||
|
@ -126,26 +126,32 @@
|
|||
#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* False Hardware Error when RETI points to invalid memory */
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
#define ANOMALY_05000120 (0)
|
||||
#define ANOMALY_05000125 (0)
|
||||
#define ANOMALY_05000149 (0)
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000250 (0)
|
||||
#define ANOMALY_05000254 (0)
|
||||
#define ANOMALY_05000257 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
|
@ -166,5 +172,7 @@
|
|||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000456 (0)
|
||||
#define ANOMALY_05000450 (0)
|
||||
#define ANOMALY_05000465 (0)
|
||||
#define ANOMALY_05000467 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
#define BF538_FAMILY
|
||||
|
||||
#include "bf538.h"
|
||||
#include "mem_map.h"
|
||||
#include "defBF539.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
|
|
|
@ -1,38 +1,16 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/mach-bf538/mem_map.h
|
||||
* Based on:
|
||||
* Author:
|
||||
* BF538 memory map
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_538_H_
|
||||
#define _MEM_MAP_538_H_
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||
|
@ -93,21 +71,4 @@
|
|||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
|
||||
/* Level 2 Memory - none */
|
||||
|
||||
#define L2_START 0
|
||||
#define L2_LENGTH 0
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
#define L1_SCRATCH_START 0xFFB00000
|
||||
#define L1_SCRATCH_LENGTH 0x1000
|
||||
|
||||
#define GET_PDA_SAFE(preg) \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda;
|
||||
|
||||
#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
||||
|
||||
#endif /* _MEM_MAP_538_H_ */
|
||||
#endif
|
||||
|
|
|
@ -76,7 +76,6 @@ static struct resource bfin_isp1760_resources[] = {
|
|||
|
||||
static struct isp1760_platform_data isp1760_priv = {
|
||||
.is_isp1761 = 0,
|
||||
.port1_disable = 0,
|
||||
.bus_width_16 = 1,
|
||||
.port1_otg = 0,
|
||||
.analog_oc = 0,
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
# error will not work on BF548 silicon version 0.0, or 0.1
|
||||
#endif
|
||||
|
||||
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1)
|
||||
|
@ -30,17 +30,17 @@
|
|||
#define ANOMALY_05000265 (1)
|
||||
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
||||
#define ANOMALY_05000272 (1)
|
||||
/* False Hardware Error Exception When ISR Context Is Not Restored */
|
||||
/* False Hardware Error Exception when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
|
||||
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
|
||||
#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
|
||||
/* TWI Slave Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
|
||||
/* External FIFO Boot Mode Is Not Functional */
|
||||
/* FIFO Boot Mode Not Functional */
|
||||
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
|
||||
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
|
||||
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
|
||||
|
@ -178,8 +178,12 @@
|
|||
#define ANOMALY_05000450 (1)
|
||||
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
|
||||
#define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
|
||||
/* False Hardware Error when RETI points to invalid memory */
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* USB Rx DMA hang */
|
||||
#define ANOMALY_05000465 (1)
|
||||
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
|
||||
#define ANOMALY_05000467 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
|
@ -189,30 +193,36 @@
|
|||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000179 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000244 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000250 (0)
|
||||
#define ANOMALY_05000254 (0)
|
||||
#define ANOMALY_05000257 (0)
|
||||
#define ANOMALY_05000261 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000283 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000301 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000315 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000362 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
#define _MACH_BLACKFIN_H_
|
||||
|
||||
#include "bf548.h"
|
||||
#include "mem_map.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
#ifdef CONFIG_BF542
|
||||
|
|
|
@ -1,38 +1,16 @@
|
|||
/*
|
||||
* file: include/asm-blackfin/mach-bf548/mem_map.h
|
||||
* based on:
|
||||
* author:
|
||||
* BF548 memory map
|
||||
*
|
||||
* created:
|
||||
* description:
|
||||
* Memory MAP Common header file for blackfin BF537/6/4 of processors.
|
||||
* rev:
|
||||
*
|
||||
* modified:
|
||||
*
|
||||
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* this program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the gnu general public license as published by
|
||||
* the free software foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* this program is distributed in the hope that it will be useful,
|
||||
* but without any warranty; without even the implied warranty of
|
||||
* merchantability or fitness for a particular purpose. see the
|
||||
* gnu general public license for more details.
|
||||
*
|
||||
* you should have received a copy of the gnu general public license
|
||||
* along with this program; see the file copying.
|
||||
* if not, write to the free software foundation,
|
||||
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_548_H_
|
||||
#define _MEM_MAP_548_H_
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
|
||||
|
@ -103,15 +81,4 @@
|
|||
# define L2_LENGTH 0x20000
|
||||
#endif
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
#define L1_SCRATCH_START 0xFFB00000
|
||||
#define L1_SCRATCH_LENGTH 0x1000
|
||||
|
||||
#define GET_PDA_SAFE(preg) \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda;
|
||||
|
||||
#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
||||
|
||||
#endif/* _MEM_MAP_548_H_ */
|
||||
#endif
|
||||
|
|
|
@ -62,7 +62,6 @@ static struct resource bfin_isp1760_resources[] = {
|
|||
|
||||
static struct isp1760_platform_data isp1760_priv = {
|
||||
.is_isp1761 = 0,
|
||||
.port1_disable = 0,
|
||||
.bus_width_16 = 1,
|
||||
.port1_otg = 0,
|
||||
.analog_oc = 0,
|
||||
|
|
|
@ -18,19 +18,19 @@
|
|||
# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
|
||||
#endif
|
||||
|
||||
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
|
||||
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
|
||||
/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
|
||||
/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
|
||||
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
|
||||
/* Testset instructions restricted to 32-bit aligned memory locations */
|
||||
/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
|
||||
#define ANOMALY_05000120 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* Erroneous exception when enabling cache */
|
||||
/* Erroneous Exception when Enabling Cache */
|
||||
#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
|
||||
/* Signbits instruction not functional under certain conditions */
|
||||
/* SIGNBITS Instruction Not Functional under Certain Conditions */
|
||||
#define ANOMALY_05000127 (1)
|
||||
/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
|
||||
#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
|
||||
|
@ -40,7 +40,7 @@
|
|||
#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
|
||||
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
|
||||
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
|
||||
/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
|
||||
/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
|
||||
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
|
||||
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
|
||||
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
|
||||
|
@ -52,7 +52,7 @@
|
|||
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
|
||||
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
|
||||
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
|
||||
/* IMDMA S1/D1 channel may stall */
|
||||
/* IMDMA S1/D1 Channel May Stall */
|
||||
#define ANOMALY_05000149 (1)
|
||||
/* DMA engine may lose data due to incorrect handshaking */
|
||||
#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
|
||||
|
@ -66,7 +66,7 @@
|
|||
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
|
||||
/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
|
||||
#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
|
||||
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
|
||||
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
|
||||
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
|
||||
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
|
||||
#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
|
||||
|
@ -76,17 +76,17 @@
|
|||
#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
|
||||
/* DMEM_CONTROL<12> is not set on Reset */
|
||||
#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT transmit data is not gated by external frame sync in certain conditions */
|
||||
/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
|
||||
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
|
||||
/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
#define ANOMALY_05000166 (1)
|
||||
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
|
||||
#define ANOMALY_05000167 (1)
|
||||
/* SDRAM auto-refresh and subsequent Power Ups */
|
||||
/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
|
||||
#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
|
||||
/* DATA CPLB page miss can result in lost write-through cache data writes */
|
||||
/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
|
||||
#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
|
||||
/* Boot-ROM code modifies SICA_IWRx wakeup registers */
|
||||
/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
|
||||
#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
|
||||
/* DSPID register values incorrect */
|
||||
#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
|
||||
|
@ -96,29 +96,29 @@
|
|||
#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
|
||||
/* Overlapping Sequencer and Memory Stalls */
|
||||
#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
|
||||
/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
|
||||
/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
|
||||
#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
|
||||
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
|
||||
#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
|
||||
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
|
||||
#define ANOMALY_05000180 (1)
|
||||
/* Disabling the PPI resets the PPI configuration registers */
|
||||
/* Disabling the PPI Resets the PPI Configuration Registers */
|
||||
#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
|
||||
/* IMDMA does not operate to full speed for 600MHz and higher devices */
|
||||
/* Internal Memory DMA Does Not Operate at Full Speed */
|
||||
#define ANOMALY_05000182 (1)
|
||||
/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
|
||||
/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
|
||||
#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
|
||||
/* PPI TX Mode with 2 External Frame Syncs */
|
||||
/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
|
||||
#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
|
||||
/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
|
||||
/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
|
||||
#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
|
||||
/* IMDMA Corrupted Data after a Halt */
|
||||
#define ANOMALY_05000187 (1)
|
||||
/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
|
||||
#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
|
||||
/* False Protection Exceptions */
|
||||
/* False Protection Exceptions when Speculative Fetch Is Cancelled */
|
||||
#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
|
||||
/* PPI not functional at core voltage < 1Volt */
|
||||
/* PPI Not Functional at Core Voltage < 1Volt */
|
||||
#define ANOMALY_05000190 (1)
|
||||
/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
|
||||
#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
|
||||
|
@ -126,7 +126,7 @@
|
|||
#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
|
||||
/* Restarting SPORT in Specific Modes May Cause Data Corruption */
|
||||
#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
|
||||
/* Failing MMR Accesses When Stalled by Preceding Memory Read */
|
||||
/* Failing MMR Accesses when Preceding Memory Read Stalls */
|
||||
#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
|
||||
/* Current DMA Address Shows Wrong Value During Carry Fix */
|
||||
#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
|
||||
|
@ -134,9 +134,9 @@
|
|||
#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
|
||||
/* Possible Infinite Stall with Specific Dual-DAG Situation */
|
||||
#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
|
||||
/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
|
||||
/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
|
||||
#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
|
||||
/* Specific sequence that can cause DMA error or DMA stopping */
|
||||
/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
|
||||
#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
|
||||
/* Recovery from "Brown-Out" Condition */
|
||||
#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
|
||||
|
@ -158,7 +158,7 @@
|
|||
#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
|
||||
/* UART STB Bit Incorrectly Affects Receiver Setting */
|
||||
#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
|
||||
/* SPORT data transmit lines are incorrectly driven in multichannel mode */
|
||||
/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
|
||||
#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
|
||||
/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
|
||||
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
|
||||
|
@ -166,7 +166,7 @@
|
|||
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
|
||||
/* TESTSET operation forces stall on the other core */
|
||||
/* TESTSET Operation Forces Stall on the Other Core */
|
||||
#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
|
||||
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
|
||||
#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
|
||||
|
@ -192,9 +192,9 @@
|
|||
#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
|
||||
/* IMDMA destination IRQ status must be read prior to using IMDMA */
|
||||
/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
|
||||
#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
|
||||
/* IMDMA may corrupt data under certain conditions */
|
||||
/* IMDMA May Corrupt Data under Certain Conditions */
|
||||
#define ANOMALY_05000267 (1)
|
||||
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
|
||||
#define ANOMALY_05000269 (1)
|
||||
|
@ -202,7 +202,7 @@
|
|||
#define ANOMALY_05000270 (1)
|
||||
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
||||
#define ANOMALY_05000272 (1)
|
||||
/* Data cache write back to external synchronous memory may be lost */
|
||||
/* Data Cache Write Back to External Synchronous Memory May Be Lost */
|
||||
#define ANOMALY_05000274 (1)
|
||||
/* PPI Timing and Sampling Information Updates */
|
||||
#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
|
||||
|
@ -212,17 +212,17 @@
|
|||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
|
||||
/* False Hardware Error Exception When ISR Context Is Not Restored */
|
||||
/* False Hardware Error Exception when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
|
||||
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
|
||||
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
|
||||
#define ANOMALY_05000283 (1)
|
||||
/* A read will receive incorrect data under certain conditions */
|
||||
/* Reads Will Receive Incorrect Data under Certain Conditions */
|
||||
#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
|
||||
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
|
||||
#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
|
||||
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
|
||||
#define ANOMALY_05000301 (1)
|
||||
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
|
||||
/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
|
||||
#define ANOMALY_05000302 (1)
|
||||
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
|
||||
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
|
||||
|
@ -230,25 +230,25 @@
|
|||
#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (1)
|
||||
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
|
||||
#define ANOMALY_05000313 (1)
|
||||
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
|
||||
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
|
||||
#define ANOMALY_05000315 (1)
|
||||
/* PF2 Output Remains Asserted After SPI Master Boot */
|
||||
/* PF2 Output Remains Asserted after SPI Master Boot */
|
||||
#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
|
||||
/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
|
||||
/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
|
||||
#define ANOMALY_05000323 (1)
|
||||
/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
|
||||
/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
|
||||
#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
|
||||
/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
|
||||
/* 24-Bit SPI Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
|
||||
/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
|
||||
/* Slave SPI Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
|
||||
/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
|
||||
/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
|
||||
#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
|
||||
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
|
||||
/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
|
||||
#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
|
||||
/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
|
||||
#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
|
||||
|
@ -276,7 +276,7 @@
|
|||
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* False Hardware Error when RETI points to invalid memory */
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
|
@ -284,6 +284,7 @@
|
|||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
|
@ -298,5 +299,7 @@
|
|||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000456 (0)
|
||||
#define ANOMALY_05000450 (0)
|
||||
#define ANOMALY_05000465 (0)
|
||||
#define ANOMALY_05000467 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
#define BF561_FAMILY
|
||||
|
||||
#include "bf561.h"
|
||||
#include "mem_map.h"
|
||||
#include "defBF561.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
|
|
|
@ -1,13 +1,16 @@
|
|||
/*
|
||||
* Memory MAP
|
||||
* Common header file for blackfin BF561 of processors.
|
||||
* BF561 memory map
|
||||
*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MEM_MAP_561_H_
|
||||
#define _MEM_MAP_561_H_
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
|
||||
|
@ -82,9 +85,6 @@
|
|||
#define COREA_L1_SCRATCH_START 0xFFB00000
|
||||
#define COREB_L1_SCRATCH_START 0xFF700000
|
||||
|
||||
#define L1_SCRATCH_START COREA_L1_SCRATCH_START
|
||||
#define L1_SCRATCH_LENGTH 0x1000
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
|
@ -155,14 +155,42 @@
|
|||
dreg = ROT dreg BY -1; \
|
||||
dreg = CC;
|
||||
|
||||
#else
|
||||
#define GET_PDA_SAFE(preg) \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda;
|
||||
static inline unsigned long get_l1_scratch_start_cpu(int cpu)
|
||||
{
|
||||
return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
|
||||
}
|
||||
static inline unsigned long get_l1_code_start_cpu(int cpu)
|
||||
{
|
||||
return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
|
||||
}
|
||||
static inline unsigned long get_l1_data_a_start_cpu(int cpu)
|
||||
{
|
||||
return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
|
||||
}
|
||||
static inline unsigned long get_l1_data_b_start_cpu(int cpu)
|
||||
{
|
||||
return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
|
||||
}
|
||||
|
||||
static inline unsigned long get_l1_scratch_start(void)
|
||||
{
|
||||
return get_l1_scratch_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline unsigned long get_l1_code_start(void)
|
||||
{
|
||||
return get_l1_code_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline unsigned long get_l1_data_a_start(void)
|
||||
{
|
||||
return get_l1_data_a_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline unsigned long get_l1_data_b_start(void)
|
||||
{
|
||||
return get_l1_data_b_start_cpu(blackfin_core_id());
|
||||
}
|
||||
|
||||
#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _MEM_MAP_533_H_ */
|
||||
#endif
|
||||
|
|
|
@ -74,7 +74,7 @@
|
|||
|
||||
/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
|
||||
#if ANOMALY_05000220 && \
|
||||
((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \
|
||||
(!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB)))
|
||||
((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \
|
||||
(!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK)))
|
||||
# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.
|
||||
#endif
|
||||
|
|
|
@ -141,7 +141,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
|
|||
sclk = get_sclk() / 1000;
|
||||
|
||||
#if ANOMALY_05000273 || ANOMALY_05000274 || \
|
||||
(!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE))
|
||||
(!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
|
||||
min_cclk = sclk * 2;
|
||||
#else
|
||||
min_cclk = sclk;
|
||||
|
|
|
@ -1609,6 +1609,7 @@ ENTRY(_sys_call_table)
|
|||
.long _sys_preadv
|
||||
.long _sys_pwritev
|
||||
.long _sys_rt_tgsigqueueinfo
|
||||
.long _sys_perf_counter_open
|
||||
|
||||
.rept NR_syscalls-(.-_sys_call_table)/4
|
||||
.long _sys_ni_syscall
|
||||
|
|
|
@ -1052,35 +1052,34 @@ int __init init_arch_irq(void)
|
|||
set_irq_chained_handler(irq, bfin_demux_error_irq);
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_TICKSOURCE_GPTMR0)
|
||||
case IRQ_TIMER0:
|
||||
set_irq_handler(irq, handle_percpu_irq);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SMP
|
||||
case IRQ_SUPPLE_0:
|
||||
case IRQ_SUPPLE_1:
|
||||
set_irq_handler(irq, handle_percpu_irq);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
#ifdef CONFIG_IPIPE
|
||||
/*
|
||||
* We want internal interrupt sources to be
|
||||
* masked, because ISRs may trigger interrupts
|
||||
* recursively (e.g. DMA), but interrupts are
|
||||
* _not_ masked at CPU level. So let's handle
|
||||
* most of them as level interrupts, except
|
||||
* the timer interrupt which is special.
|
||||
*/
|
||||
if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR)
|
||||
set_irq_handler(irq, handle_simple_irq);
|
||||
else
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
#else /* !CONFIG_IPIPE */
|
||||
#ifndef CONFIG_TICKSOURCE_CORETMR
|
||||
case IRQ_TIMER0:
|
||||
set_irq_handler(irq, handle_simple_irq);
|
||||
#endif /* !CONFIG_IPIPE */
|
||||
break;
|
||||
#endif /* !CONFIG_TICKSOURCE_CORETMR */
|
||||
case IRQ_CORETMR:
|
||||
set_irq_handler(irq, handle_simple_irq);
|
||||
break;
|
||||
default:
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
break;
|
||||
#else /* !CONFIG_IPIPE */
|
||||
#ifdef CONFIG_TICKSOURCE_GPTMR0
|
||||
case IRQ_TIMER0:
|
||||
set_irq_handler(irq, handle_percpu_irq);
|
||||
break;
|
||||
#endif /* CONFIG_TICKSOURCE_GPTMR0 */
|
||||
default:
|
||||
set_irq_handler(irq, handle_simple_irq);
|
||||
break;
|
||||
#endif /* !CONFIG_IPIPE */
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1224,15 +1223,14 @@ __attribute__((l1_text))
|
|||
asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
|
||||
{
|
||||
struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
|
||||
struct ipipe_domain *this_domain = ipipe_current_domain;
|
||||
struct ipipe_domain *this_domain = __ipipe_current_domain;
|
||||
struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
|
||||
struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
|
||||
int irq, s;
|
||||
|
||||
if (likely(vec == EVT_IVTMR_P)) {
|
||||
if (likely(vec == EVT_IVTMR_P))
|
||||
irq = IRQ_CORETMR;
|
||||
|
||||
} else {
|
||||
else {
|
||||
#if defined(SIC_ISR0) || defined(SICA_ISR0)
|
||||
unsigned long sic_status[3];
|
||||
|
||||
|
@ -1262,12 +1260,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
|
|||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
irq = ivg->irqno;
|
||||
}
|
||||
|
||||
if (irq == IRQ_SYSTMR) {
|
||||
#ifndef CONFIG_GENERIC_CLOCKEVENTS
|
||||
#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
|
||||
bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
|
||||
#endif
|
||||
/* This is basically what we need from the register frame. */
|
||||
|
|
|
@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BFIN_WB
|
||||
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
|
||||
static void flushinv_all_dcache(void)
|
||||
{
|
||||
u32 way, bank, subbank, set;
|
||||
|
@ -175,7 +175,7 @@ static inline void dcache_disable(void)
|
|||
#ifdef CONFIG_BFIN_DCACHE
|
||||
unsigned long ctrl;
|
||||
|
||||
#ifdef CONFIG_BFIN_WB
|
||||
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
|
||||
flushinv_all_dcache();
|
||||
#endif
|
||||
SSYNC();
|
||||
|
|
|
@ -160,7 +160,7 @@ void __init mem_init(void)
|
|||
|
||||
/* do not count in kernel image between _rambase and _ramstart */
|
||||
reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
|
||||
#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
|
||||
#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
|
||||
reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT;
|
||||
#endif
|
||||
|
||||
|
|
Loading…
Reference in a new issue