ASoC: wm_adsp: Factor out ADSP2 boot proceedure
Move the ADSP2 boot proceedure into a work structure in preparation for running it asynchronously with the reset of the audio path bring up. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@linaro.org>hifive-unleashed-5.1
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5095f55d7c
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d8a64d6ade
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@ -1492,6 +1492,105 @@ static int wm_adsp2_ena(struct wm_adsp *dsp)
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return 0;
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return 0;
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}
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}
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void wm_adsp2_boot_work(struct work_struct *work)
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{
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struct wm_adsp *dsp = container_of(work,
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struct wm_adsp,
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boot_work);
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int ret;
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unsigned int val;
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/*
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* For simplicity set the DSP clock rate to be the
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* SYSCLK rate rather than making it configurable.
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*/
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ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
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if (ret != 0) {
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adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
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return;
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}
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val = (val & ARIZONA_SYSCLK_FREQ_MASK)
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>> ARIZONA_SYSCLK_FREQ_SHIFT;
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ret = regmap_update_bits_async(dsp->regmap,
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dsp->base + ADSP2_CLOCKING,
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ADSP2_CLK_SEL_MASK, val);
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if (ret != 0) {
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adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
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return;
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}
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if (dsp->dvfs) {
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ret = regmap_read(dsp->regmap,
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dsp->base + ADSP2_CLOCKING, &val);
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if (ret != 0) {
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dev_err(dsp->dev, "Failed to read clocking: %d\n", ret);
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return;
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}
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if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
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ret = regulator_enable(dsp->dvfs);
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if (ret != 0) {
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dev_err(dsp->dev,
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"Failed to enable supply: %d\n",
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ret);
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return;
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}
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ret = regulator_set_voltage(dsp->dvfs,
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1800000,
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1800000);
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if (ret != 0) {
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dev_err(dsp->dev,
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"Failed to raise supply: %d\n",
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ret);
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return;
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}
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}
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}
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ret = wm_adsp2_ena(dsp);
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if (ret != 0)
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return;
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ret = wm_adsp_load(dsp);
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if (ret != 0)
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goto err;
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ret = wm_adsp_setup_algs(dsp);
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if (ret != 0)
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goto err;
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ret = wm_adsp_load_coeff(dsp);
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if (ret != 0)
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goto err;
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/* Initialize caches for enabled and unset controls */
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ret = wm_coeff_init_control_caches(dsp);
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if (ret != 0)
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goto err;
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/* Sync set controls */
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ret = wm_coeff_sync_controls(dsp);
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if (ret != 0)
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goto err;
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ret = regmap_update_bits_async(dsp->regmap,
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dsp->base + ADSP2_CONTROL,
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ADSP2_CORE_ENA,
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ADSP2_CORE_ENA);
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if (ret != 0)
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goto err;
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dsp->running = true;
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return;
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err:
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regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
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ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
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}
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int wm_adsp2_event(struct snd_soc_dapm_widget *w,
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int wm_adsp2_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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struct snd_kcontrol *kcontrol, int event)
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{
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{
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@ -1500,99 +1599,24 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
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struct wm_adsp *dsp = &dsps[w->shift];
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struct wm_adsp *dsp = &dsps[w->shift];
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struct wm_adsp_alg_region *alg_region;
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struct wm_adsp_alg_region *alg_region;
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struct wm_coeff_ctl *ctl;
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struct wm_coeff_ctl *ctl;
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unsigned int val;
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int ret;
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int ret;
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dsp->card = codec->card;
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dsp->card = codec->card;
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switch (event) {
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switch (event) {
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMU:
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/*
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queue_work(system_unbound_wq, &dsp->boot_work);
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* For simplicity set the DSP clock rate to be the
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flush_work(&dsp->boot_work);
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* SYSCLK rate rather than making it configurable.
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*/
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ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
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if (ret != 0) {
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adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
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ret);
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return ret;
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}
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val = (val & ARIZONA_SYSCLK_FREQ_MASK)
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>> ARIZONA_SYSCLK_FREQ_SHIFT;
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ret = regmap_update_bits_async(dsp->regmap,
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if (!dsp->running)
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dsp->base + ADSP2_CLOCKING,
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return -EIO;
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ADSP2_CLK_SEL_MASK, val);
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if (ret != 0) {
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adsp_err(dsp, "Failed to set clock rate: %d\n",
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ret);
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return ret;
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}
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if (dsp->dvfs) {
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ret = regmap_update_bits(dsp->regmap,
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ret = regmap_read(dsp->regmap,
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dsp->base + ADSP2_CONTROL,
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dsp->base + ADSP2_CLOCKING, &val);
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ADSP2_START,
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if (ret != 0) {
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ADSP2_START);
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dev_err(dsp->dev,
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"Failed to read clocking: %d\n", ret);
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return ret;
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}
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if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
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ret = regulator_enable(dsp->dvfs);
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if (ret != 0) {
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dev_err(dsp->dev,
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"Failed to enable supply: %d\n",
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ret);
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return ret;
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}
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ret = regulator_set_voltage(dsp->dvfs,
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1800000,
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1800000);
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if (ret != 0) {
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dev_err(dsp->dev,
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"Failed to raise supply: %d\n",
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ret);
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return ret;
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}
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}
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}
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ret = wm_adsp2_ena(dsp);
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if (ret != 0)
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return ret;
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ret = wm_adsp_load(dsp);
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if (ret != 0)
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if (ret != 0)
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goto err;
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goto err;
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ret = wm_adsp_setup_algs(dsp);
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if (ret != 0)
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goto err;
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ret = wm_adsp_load_coeff(dsp);
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if (ret != 0)
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goto err;
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/* Initialize caches for enabled and unset controls */
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ret = wm_coeff_init_control_caches(dsp);
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if (ret != 0)
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goto err;
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/* Sync set controls */
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ret = wm_coeff_sync_controls(dsp);
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if (ret != 0)
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goto err;
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ret = regmap_update_bits_async(dsp->regmap,
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dsp->base + ADSP2_CONTROL,
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ADSP2_CORE_ENA | ADSP2_START,
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ADSP2_CORE_ENA | ADSP2_START);
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if (ret != 0)
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goto err;
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dsp->running = true;
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break;
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break;
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case SND_SOC_DAPM_PRE_PMD:
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case SND_SOC_DAPM_PRE_PMD:
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@ -1663,6 +1687,7 @@ int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
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INIT_LIST_HEAD(&adsp->alg_regions);
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INIT_LIST_HEAD(&adsp->alg_regions);
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INIT_LIST_HEAD(&adsp->ctl_list);
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INIT_LIST_HEAD(&adsp->ctl_list);
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INIT_WORK(&adsp->boot_work, wm_adsp2_boot_work);
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if (dvfs) {
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if (dvfs) {
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adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
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adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
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@ -59,6 +59,8 @@ struct wm_adsp {
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struct regulator *dvfs;
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struct regulator *dvfs;
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struct list_head ctl_list;
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struct list_head ctl_list;
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struct work_struct boot_work;
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};
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};
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#define WM_ADSP1(wname, num) \
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#define WM_ADSP1(wname, num) \
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