Merge remote-tracking branch 'origin/display/ldb' into display/next
* origin/display/ldb: (11 commits) drm/imx: ldb: Add dual channel mode support for i.MX8QXP dt-bindings: display: imx: ldb: Add i.MX8qxp LDB dual channel mode documentation dt-bindings: display: imx: ldb: Correct pixel and bypass clock description drm/imx: ldb: Add system power management support MLK-21876-23 drm/imx: ldb: fix incorrect color displayed for mx8qxp ...5.4-rM2-2.2.x-imx-squashed
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d8a6ae95b3
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@ -9,15 +9,24 @@ nodes describing each of the two LVDS encoder channels of the bridge.
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Required properties:
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- #address-cells : should be <1>
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- #size-cells : should be <0>
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- compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
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Both LDB versions are similar, but i.MX6 has an additional
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multiplexer in the front to select any of the four IPU display
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interfaces as input for each LVDS channel.
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- compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or
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"fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb".
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All LDB versions are similar.
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i.MX6q/dl has an additional multiplexer in the front to select
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any of the two or four IPU display interfaces as input for each
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LVDS channel.
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i.MX8qm LDB supports 10bit RGB input and needs an additional
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phy.
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i.MX8qxp LDB only supports one LVDS encoder channel(either
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channel0 or channel1).
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- gpr : should be <&gpr> on i.MX53 and i.MX6q.
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The phandle points to the iomuxc-gpr region containing the LVDS
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control register.
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- fsl,auxldb : phandle to auxiliary LDB which is used in dual channel mode.
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Only required by i.MX8qxp.
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- clocks, clock-names : phandles to the LDB divider and selector clocks and to
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the display interface selector clocks, as described in
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the display interface selector clocks or pixel and
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bypass clocks as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The following clocks are expected on i.MX53:
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"di0_pll" - LDB LVDS channel 0 mux
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@ -29,14 +38,25 @@ Required properties:
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On i.MX6q the following additional clocks are needed:
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"di2_sel" - IPU2 DI0 mux
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"di3_sel" - IPU2 DI1 mux
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The following clocks are expected on i.MX8qm and i.MX8qxp:
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"pixel" - pixel clock
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"bypass" - bypass clock
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The following clocks are expected on i.MX8qxp:
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"aux_pixel" - auxiliary pixel clock in dual channel mode
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"aux_bypass" - auxiliary bypass clock in dual channel mode
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The needed clock numbers for each are documented in
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Documentation/devicetree/bindings/clock/imx5-clock.txt, and in
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Documentation/devicetree/bindings/clock/imx6q-clock.txt.
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Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in
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Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt, and in
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Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
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- power-domains : phandle pointing to power domain, only required by i.MX8qm and
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i.MX8qxp.
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Optional properties:
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- pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
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- pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm
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and i.MX8qxp
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- pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
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not used on i.MX6q
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not used on i.MX6q, i.MX8qm and i.MX8qxp
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- fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
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be configured - one input will be distributed on both outputs in dual
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channel mode
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@ -57,9 +77,14 @@ Required properties:
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(lvds-channel@[0,1], respectively).
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On i.MX6, there should be four input ports (port@[0-3]) that correspond
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to the four LVDS multiplexer inputs.
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A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
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to a panel input port. Optionally, the output port can be left out if
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display-timings are used instead.
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On i.MX8qm, the two channels of LDB connect to one display interface of DPU.
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A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm
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and i.MX8qxp) must be connected to a panel input port or a bridge input port.
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Optionally, the output port can be left out if display-timings are used
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instead.
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- phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm and
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i.MX8qxp.
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- phy-names: should be "ldb_phy". Valid only on i.MX8qm and i.MX8qxp.
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Optional properties (required if display-timings are used):
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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@ -69,6 +94,7 @@ Optional properties (required if display-timings are used):
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This describes how the color bits are laid out in the
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serialized LVDS signal.
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- fsl,data-width : should be <18> or <24>
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Additionally, <30> for i.MX8qm.
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example:
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@ -29,9 +29,18 @@ config DRM_IMX_LDB
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tristate "Support for LVDS displays"
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depends on DRM_IMX && MFD_SYSCON
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select DRM_PANEL
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select PHY_MIXEL_LVDS
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select PHY_MIXEL_LVDS_COMBO
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help
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Choose this to enable the internal LVDS Display Bridge (LDB)
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found on i.MX53 and i.MX6 processors.
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found on i.MX53, i.MX6 and i.MX8 processors.
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config DRM_IMX_IPUV3
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tristate
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depends on DRM_IMX
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depends on IMX_IPUV3_CORE
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default y if DRM_IMX=y
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default m if DRM_IMX=m
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config DRM_IMX_IPUV3
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tristate
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