Merge remote-tracking branch 'origin/display/ldb' into display/next

* origin/display/ldb: (11 commits)
  drm/imx: ldb: Add dual channel mode support for i.MX8QXP
  dt-bindings: display: imx: ldb: Add i.MX8qxp LDB dual channel mode documentation
  dt-bindings: display: imx: ldb: Correct pixel and bypass clock description
  drm/imx: ldb: Add system power management support
  MLK-21876-23 drm/imx: ldb: fix incorrect color displayed for mx8qxp
  ...

Documentation/devicetree/bindings/display/imx/ldb.txt

@@ -9,15 +9,24 @@ nodes describing each of the two LVDS encoder channels of the bridge.
 Required properties:
  - #address-cells : should be <1>
  - #size-cells : should be <0>
- - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
+ - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or
-                Both LDB versions are similar, but i.MX6 has an additional
+                "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb".
-                multiplexer in the front to select any of the four IPU display
+                All LDB versions are similar.
-                interfaces as input for each LVDS channel.
+                i.MX6q/dl has an additional multiplexer in the front to select
+                any of the two or four IPU display interfaces as input for each
+                LVDS channel.
+                i.MX8qm LDB supports 10bit RGB input and needs an additional
+                phy.
+                i.MX8qxp LDB only supports one LVDS encoder channel(either
+                channel0 or channel1).
  - gpr : should be <&gpr> on i.MX53 and i.MX6q.
          The phandle points to the iomuxc-gpr region containing the LVDS
          control register.
+ - fsl,auxldb : phandle to auxiliary LDB which is used in dual channel mode.
+                Only required by i.MX8qxp.
 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
-                        the display interface selector clocks, as described in
+                        the display interface selector clocks or pixel and
+                        bypass clocks as described in
                         Documentation/devicetree/bindings/clock/clock-bindings.txt
         The following clocks are expected on i.MX53:
                 "di0_pll" - LDB LVDS channel 0 mux
@@ -29,14 +38,25 @@ Required properties:
         On i.MX6q the following additional clocks are needed:
                 "di2_sel" - IPU2 DI0 mux
                 "di3_sel" - IPU2 DI1 mux
+        The following clocks are expected on i.MX8qm and i.MX8qxp:
+                "pixel" - pixel clock
+                "bypass" - bypass clock
+        The following clocks are expected on i.MX8qxp:
+                "aux_pixel" - auxiliary pixel clock in dual channel mode
+                "aux_bypass" - auxiliary bypass clock in dual channel mode
         The needed clock numbers for each are documented in
         Documentation/devicetree/bindings/clock/imx5-clock.txt, and in
-        Documentation/devicetree/bindings/clock/imx6q-clock.txt.
+        Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in
+        Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt, and in
+        Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
+- power-domains : phandle pointing to power domain, only required by i.MX8qm and
+                  i.MX8qxp.
 
 Optional properties:
- - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
+ - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm
+                   and i.MX8qxp
  - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
-               not used on i.MX6q
+               not used on i.MX6q, i.MX8qm and i.MX8qxp
  - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
    be configured - one input will be distributed on both outputs in dual
    channel mode
@@ -57,9 +77,14 @@ Required properties:
    (lvds-channel@[0,1], respectively).
    On i.MX6, there should be four input ports (port@[0-3]) that correspond
    to the four LVDS multiplexer inputs.
-   A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
+   On i.MX8qm, the two channels of LDB connect to one display interface of DPU.
-   to a panel input port. Optionally, the output port can be left out if
+   A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm
-   display-timings are used instead.
+   and i.MX8qxp) must be connected to a panel input port or a bridge input port.
+   Optionally, the output port can be left out if display-timings are used
+   instead.
+ - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm and
+         i.MX8qxp.
+ - phy-names: should be "ldb_phy". Valid only on i.MX8qm and i.MX8qxp.
 
 Optional properties (required if display-timings are used):
  - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -69,6 +94,7 @@ Optional properties (required if display-timings are used):
                       This describes how the color bits are laid out in the
                       serialized LVDS signal.
  - fsl,data-width : should be <18> or <24>
+                    Additionally, <30> for i.MX8qm.
 
 example:
 

drivers/gpu/drm/imx/Kconfig

@@ -29,9 +29,18 @@ config DRM_IMX_LDB
 	tristate "Support for LVDS displays"
 	depends on DRM_IMX && MFD_SYSCON
 	select DRM_PANEL
+	select PHY_MIXEL_LVDS
+	select PHY_MIXEL_LVDS_COMBO
 	help
 	  Choose this to enable the internal LVDS Display Bridge (LDB)
-	  found on i.MX53 and i.MX6 processors.
+	  found on i.MX53, i.MX6 and i.MX8 processors.
+
+config DRM_IMX_IPUV3
+	tristate
+	depends on DRM_IMX
+	depends on IMX_IPUV3_CORE
+	default y if DRM_IMX=y
+	default m if DRM_IMX=m
 
 config DRM_IMX_IPUV3
 	tristate