serial: sh-sci: Standardize on using the BIT() macro to define register bits
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>hifive-unleashed-5.1
Geert Uytterhoeven
Greg Kroah-Hartman
parent
31f90796c6
commit
d94a0a3857
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@ -1,3 +1,4 @@
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#include <linux/bitops.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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@ -32,62 +33,62 @@ enum {
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/* SCSMR (Serial Mode Register) */
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#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
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#define SCSMR_PE (1 << 5) /* Parity Enable */
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#define SCSMR_ODD (1 << 4) /* Odd Parity */
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#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
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#define SCSMR_CKS 0x0003 /* Clock Select */
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#define SCSMR_CHR BIT(6) /* 7-bit Character Length */
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#define SCSMR_PE BIT(5) /* Parity Enable */
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#define SCSMR_ODD BIT(4) /* Odd Parity */
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#define SCSMR_STOP BIT(3) /* Stop Bit Length */
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#define SCSMR_CKS 0x0003 /* Clock Select */
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/* Serial Control Register, SCIFA/SCIFB only bits */
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#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
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#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
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/* SCxSR (Serial Status Register) on SCI */
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#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
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#define SCI_RDRF 0x40 /* Receive Data Register Full */
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#define SCI_ORER 0x20 /* Overrun Error */
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#define SCI_FER 0x10 /* Framing Error */
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#define SCI_PER 0x08 /* Parity Error */
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#define SCI_TEND 0x04 /* Transmit End */
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#define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
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#define SCI_RDRF BIT(6) /* Receive Data Register Full */
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#define SCI_ORER BIT(5) /* Overrun Error */
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#define SCI_FER BIT(4) /* Framing Error */
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#define SCI_PER BIT(3) /* Parity Error */
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#define SCI_TEND BIT(2) /* Transmit End */
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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/* SCxSR (Serial Status Register) on SCIF, HSCIF */
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#define SCIF_ER 0x0080 /* Receive Error */
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#define SCIF_TEND 0x0040 /* Transmission End */
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#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
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#define SCIF_BRK 0x0010 /* Break Detect */
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#define SCIF_FER 0x0008 /* Framing Error */
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#define SCIF_PER 0x0004 /* Parity Error */
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#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
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#define SCIF_DR 0x0001 /* Receive Data Ready */
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#define SCIF_ER BIT(7) /* Receive Error */
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#define SCIF_TEND BIT(6) /* Transmission End */
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#define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
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#define SCIF_BRK BIT(4) /* Break Detect */
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#define SCIF_FER BIT(3) /* Framing Error */
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#define SCIF_PER BIT(2) /* Parity Error */
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#define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
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#define SCIF_DR BIT(0) /* Receive Data Ready */
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* SCFCR (FIFO Control Register) */
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#define SCFCR_MCE 0x0008 /* Modem Control Enable */
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#define SCFCR_TFRST 0x0004 /* Transmit FIFO Data Register Reset */
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#define SCFCR_RFRST 0x0002 /* Receive FIFO Data Register Reset */
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#define SCFCR_LOOP (1 << 0) /* Loopback Test */
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#define SCFCR_MCE BIT(3) /* Modem Control Enable */
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#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
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#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
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#define SCFCR_LOOP BIT(0) /* Loopback Test */
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/* SCSPTR (Serial Port Register), optional */
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#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
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#define SCSPTR_RTSDT (1 << 6) /* Serial Port RTS Pin Data */
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#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
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#define SCSPTR_CTSDT (1 << 4) /* Serial Port CTS Pin Data */
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#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
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#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
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#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS Pin Input/Output */
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#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS Pin Data */
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#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS Pin Input/Output */
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#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS Pin Data */
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#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
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#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
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/* HSSRR HSCIF */
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#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
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#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
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/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
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#define SCPCR_RTSC (1 << 4) /* Serial Port RTS Pin / Output Pin */
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#define SCPCR_CTSC (1 << 3) /* Serial Port CTS Pin / Input Pin */
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#define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */
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#define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */
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/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
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#define SCPDR_RTSD (1 << 4) /* Serial Port RTS Output Pin Data */
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#define SCPDR_CTSD (1 << 3) /* Serial Port CTS Input Pin Data */
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#define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */
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#define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */
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#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
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@ -1,6 +1,7 @@
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#ifndef __LINUX_SERIAL_SCI_H
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#define __LINUX_SERIAL_SCI_H
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#include <linux/bitops.h>
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#include <linux/serial_core.h>
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#include <linux/sh_dma.h>
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@ -11,14 +12,14 @@
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#define SCIx_NOT_SUPPORTED (-1)
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/* Serial Control Register (@ = not supported by all parts) */
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#define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */
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#define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */
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#define SCSCR_TE (1 << 5) /* Transmit Enable */
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#define SCSCR_RE (1 << 4) /* Receive Enable */
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#define SCSCR_REIE (1 << 3) /* Receive Error Interrupt Enable @ */
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#define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable @ */
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#define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */
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#define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */
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#define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */
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#define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */
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#define SCSCR_TE BIT(5) /* Transmit Enable */
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#define SCSCR_RE BIT(4) /* Receive Enable */
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#define SCSCR_REIE BIT(3) /* Receive Error Interrupt Enable @ */
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#define SCSCR_TOIE BIT(2) /* Timeout Interrupt Enable @ */
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#define SCSCR_CKE1 BIT(1) /* Clock Enable 1 */
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#define SCSCR_CKE0 BIT(0) /* Clock Enable 0 */
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enum {
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@ -48,7 +49,7 @@ struct plat_sci_port_ops {
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/*
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* Port-specific capabilities
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*/
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#define SCIx_HAVE_RTSCTS (1 << 0)
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#define SCIx_HAVE_RTSCTS BIT(0)
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/*
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* Platform device specific platform_data struct
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