ath9k: Set appropriate bit for AR9565 in btc control register
Signed-off-by: Bala Shanmugam <bkamatch@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -850,11 +850,18 @@ int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
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SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
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SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
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SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
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SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
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SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
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if (AR_SREV_9565(ah)) {
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regval |= SM(1, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
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SM(1, AR_BTCOEX_CTRL_RX_CHAIN_MASK);
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REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
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AR_BTCOEX_CTRL2_TX_CHAIN_MASK, 0x1);
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} else {
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regval |= SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
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SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK);
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}
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REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
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