isci: Add support for user parameters in SCIC layer
Add support for the following parameters in SCIC:
/**
* This field specifies the NOTIFY (ENABLE SPIN UP) primitive
* insertion frequency for this phy index.
*/
u32 notify_enable_spin_up_insertion_frequency;
/**
* This method specifies the number of transmitted DWORDs within which
* to transmit a single ALIGN primitive. This value applies regardless
* of what type of device is attached or connection state. A value of
* 0 indicates that no ALIGN primitives will be inserted.
*/
u16 align_insertion_frequency;
/**
* This method specifies the number of transmitted DWORDs within which
* to transmit 2 ALIGN primitives. This applies for SAS connections
* only. A minimum value of 3 is required for this field.
*/
u16 in_connection_align_insertion_frequency;
Signed-off-by: Krzysztof Wierzbicki <Krzysztof.Wierzbicki@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Jacek Danecki
Dan Williams
parent
246214667f
commit
d9def184b3
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@ -616,7 +616,6 @@ void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
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scu_afe_register_write(scic, afe_bias_control, 0x00005500);
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else
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scu_afe_register_write(scic, afe_bias_control, 0x00005A00);
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scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
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@ -625,7 +624,7 @@ void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
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scu_afe_register_write(scic, afe_pll_control0, 0x80040A08);
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else
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scu_afe_register_write(scic, afe_pll_control0, 0x80040908);
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scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
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/* Wait for the PLL to lock */
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@ -1962,17 +1961,16 @@ void scic_sds_controller_release_frame(
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* configuration parameters to their default values.
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*
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*/
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static void scic_sds_controller_set_default_config_parameters(
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struct scic_sds_controller *this_controller)
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static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic)
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{
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u16 index;
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/* Default to no SSC operation. */
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this_controller->oem_parameters.sds1.controller.do_enable_ssc = false;
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scic->oem_parameters.sds1.controller.do_enable_ssc = false;
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/* Initialize all of the port parameter information to narrow ports. */
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for (index = 0; index < SCI_MAX_PORTS; index++) {
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this_controller->oem_parameters.sds1.ports[index].phy_mask = 0;
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scic->oem_parameters.sds1.ports[index].phy_mask = 0;
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}
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/* Initialize all of the phy parameter information. */
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@ -1980,24 +1978,27 @@ static void scic_sds_controller_set_default_config_parameters(
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/*
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* Default to 3G (i.e. Gen 2) for now. User can override if
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* they choose. */
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this_controller->user_parameters.sds1.phys[index].max_speed_generation = 2;
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scic->user_parameters.sds1.phys[index].max_speed_generation = 2;
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/* the frequencies cannot be 0 */
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scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
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scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
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scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
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/*
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* Previous Vitesse based expanders had a arbitration issue that
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* is worked around by having the upper 32-bits of SAS address
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* with a value greater then the Vitesse company identifier.
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* Hence, usage of 0x5FCFFFFF. */
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this_controller->oem_parameters.sds1.phys[index].sas_address.low
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= 0x00000001;
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this_controller->oem_parameters.sds1.phys[index].sas_address.high
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= 0x5FCFFFFF;
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scic->oem_parameters.sds1.phys[index].sas_address.low = 0x00000001;
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scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF;
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}
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this_controller->user_parameters.sds1.stp_inactivity_timeout = 5;
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this_controller->user_parameters.sds1.ssp_inactivity_timeout = 5;
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this_controller->user_parameters.sds1.stp_max_occupancy_timeout = 5;
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this_controller->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
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this_controller->user_parameters.sds1.no_outbound_task_timeout = 20;
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scic->user_parameters.sds1.stp_inactivity_timeout = 5;
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scic->user_parameters.sds1.ssp_inactivity_timeout = 5;
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scic->user_parameters.sds1.stp_max_occupancy_timeout = 5;
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scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
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scic->user_parameters.sds1.no_outbound_task_timeout = 20;
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}
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@ -2103,9 +2104,9 @@ u32 scic_controller_get_suggested_start_timeout(
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* per interval - 1 (once OEM parameters are supported).
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* Currently we assume only 1 phy per interval. */
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return (SCIC_SDS_SIGNATURE_FIS_TIMEOUT
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return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
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+ SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
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+ ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL));
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+ ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
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}
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/* --------------------------------------------------------------------------- */
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@ -2489,16 +2490,29 @@ enum sci_status scic_user_parameters_set(
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* Validate the user parameters. If they are not legal, then
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* return a failure. */
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for (index = 0; index < SCI_MAX_PHYS; index++) {
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if (!
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(scic_parms->sds1.phys[index].max_speed_generation
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if (!(scic_parms->sds1.phys[index].max_speed_generation
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<= SCIC_SDS_PARM_MAX_SPEED
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&& scic_parms->sds1.phys[index].max_speed_generation
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> SCIC_SDS_PARM_NO_SPEED
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)
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> SCIC_SDS_PARM_NO_SPEED))
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return SCI_FAILURE_INVALID_PARAMETER_VALUE;
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if (scic_parms->sds1.phys[index].in_connection_align_insertion_frequency < 3)
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return SCI_FAILURE_INVALID_PARAMETER_VALUE;
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if (
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(scic_parms->sds1.phys[index].in_connection_align_insertion_frequency < 3) ||
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(scic_parms->sds1.phys[index].align_insertion_frequency == 0) ||
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(scic_parms->sds1.phys[index].notify_enable_spin_up_insertion_frequency == 0)
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)
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return SCI_FAILURE_INVALID_PARAMETER_VALUE;
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}
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if ((scic_parms->sds1.stp_inactivity_timeout == 0) ||
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(scic_parms->sds1.ssp_inactivity_timeout == 0) ||
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(scic_parms->sds1.stp_max_occupancy_timeout == 0) ||
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(scic_parms->sds1.ssp_max_occupancy_timeout == 0) ||
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(scic_parms->sds1.no_outbound_task_timeout == 0))
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return SCI_FAILURE_INVALID_PARAMETER_VALUE;
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memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms));
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return SCI_SUCCESS;
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@ -125,6 +125,7 @@ static enum sci_status scic_sds_phy_link_layer_initialization(
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u32 parity_check = 0;
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u32 parity_count = 0;
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u32 link_layer_control;
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u32 clksm_value = 0;
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this_phy->link_layer_registers = link_layer_registers;
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@ -199,7 +200,20 @@ static enum sci_status scic_sds_phy_link_layer_initialization(
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SCU_SAS_PHYCAP_WRITE(this_phy, phy_capabilities.u.all);
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/* Set the enable spinup period but disable the ability to send notify enable spinup */
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SCU_SAS_ENSPINUP_WRITE(this_phy, SCU_ENSPINUP_GEN_VAL(COUNT, 0x33));
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SCU_SAS_ENSPINUP_WRITE(this_phy, SCU_ENSPINUP_GEN_VAL(COUNT,
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this_phy->owning_port->owning_controller->user_parameters.sds1.
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phys[this_phy->phy_index].notify_enable_spin_up_insertion_frequency));
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/* Write the ALIGN Insertion Ferequency for connected phy and inpendent of connected state */
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clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
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this_phy->owning_port->owning_controller->user_parameters.sds1.
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phys[this_phy->phy_index].in_connection_align_insertion_frequency);
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clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
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this_phy->owning_port->owning_controller->user_parameters.sds1.
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phys[this_phy->phy_index].align_insertion_frequency);
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SCU_SAS_CLKSM_WRITE(this_phy, clksm_value);
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#if defined(CONFIG_PBG_HBA_A0) || defined(CONFIG_PBG_HBA_A2) || defined(CONFIG_PBG_HBA_BETA)
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/* / @todo Provide a way to write this register correctly */
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@ -217,6 +217,14 @@
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#define SCU_SAS_ENSPINUP_WRITE(phy, value) \
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scu_link_layer_register_write(phy, notify_enable_spinup_control, value)
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/* This macro reads the CLKSM register */
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#define SCU_SAS_CLKSM_READ(phy) \
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scu_link_layer_register_read(phy, clock_skew_management)
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/* This macro writes the CLKSM register */
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#define SCU_SAS_CLKSM_WRITE(phy, value) \
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scu_link_layer_register_write(phy, clock_skew_management, value)
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/* / This macro reads the PHY Capacity register */
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#define SCU_SAS_PHYCAP_READ(phy) \
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scu_link_layer_register_read(phy, phy_capabilities)
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@ -611,6 +611,13 @@
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#define SCU_SAS_PCFG_GEN_BIT(name) \
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SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_ ## name)
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#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT (0)
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#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK (0x000007FF)
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#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_SHIFT (16)
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#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK (0x00ff0000)
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#define SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(name, value) \
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SCU_GEN_VALUE(SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_##name, value)
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#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT (0)
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#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK (0x0003FFFF)
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