sata_mv: introduce support for ATAPI devices
Add ATAPI support to sata_mv, using sff DMA for GEN_II chipsets, and plain old PIO for GEN_IIE. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>hifive-unleashed-5.1
Mark Lord
Jeff Garzik
parent
32cd11a610
commit
da14265e77
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@ -31,8 +31,6 @@
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*
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* --> Complete a full errata audit for all chipsets to identify others.
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*
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* --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
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*
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* --> Develop a low-power-consumption strategy, and implement it.
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*
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* --> [Experiment, low priority] Investigate interrupt coalescing.
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@ -68,7 +66,7 @@
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#include <linux/libata.h>
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#define DRV_NAME "sata_mv"
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#define DRV_VERSION "1.25"
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#define DRV_VERSION "1.26"
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enum {
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/* BAR's are enumerated in terms of pci_resource_start() terms */
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@ -126,7 +124,7 @@ enum {
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MV_GEN_II_FLAGS = MV_COMMON_FLAGS | MV_FLAG_IRQ_COALESCE |
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ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
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ATA_FLAG_NCQ | ATA_FLAG_NO_ATAPI,
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ATA_FLAG_NCQ,
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MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
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@ -348,6 +346,12 @@ enum {
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EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
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BMDMA_CMD_OFS = 0x224, /* bmdma command register */
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BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
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BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
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BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
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/* Host private flags (hp_flags) */
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MV_HP_FLAG_MSI = (1 << 0),
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MV_HP_ERRATA_50XXB0 = (1 << 1),
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@ -547,6 +551,15 @@ static void mv_pmp_error_handler(struct ata_port *ap);
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static void mv_process_crpb_entries(struct ata_port *ap,
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struct mv_port_priv *pp);
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static unsigned long mv_mode_filter(struct ata_device *dev,
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unsigned long xfer_mask);
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static void mv_sff_irq_clear(struct ata_port *ap);
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static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
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static void mv_bmdma_setup(struct ata_queued_cmd *qc);
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static void mv_bmdma_start(struct ata_queued_cmd *qc);
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static void mv_bmdma_stop(struct ata_queued_cmd *qc);
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static u8 mv_bmdma_status(struct ata_port *ap);
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/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
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* because we have to allow room for worst case splitting of
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* PRDs for 64K boundaries in mv_fill_sg().
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@ -594,6 +607,14 @@ static struct ata_port_operations mv6_ops = {
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.pmp_softreset = mv_softreset,
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.softreset = mv_softreset,
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.error_handler = mv_pmp_error_handler,
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.sff_irq_clear = mv_sff_irq_clear,
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.check_atapi_dma = mv_check_atapi_dma,
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.bmdma_setup = mv_bmdma_setup,
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.bmdma_start = mv_bmdma_start,
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.bmdma_stop = mv_bmdma_stop,
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.bmdma_status = mv_bmdma_status,
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.mode_filter = mv_mode_filter,
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};
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static struct ata_port_operations mv_iie_ops = {
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@ -1392,6 +1413,167 @@ static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
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*cmdw = cpu_to_le16(tmp);
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}
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/**
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* mv_mode_filter - Allow ATAPI DMA only on GenII chips.
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* @dev: device whose xfer modes are being configured.
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*
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* Only the GenII hardware can use DMA with ATAPI drives.
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*/
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static unsigned long mv_mode_filter(struct ata_device *adev,
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unsigned long xfer_mask)
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{
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if (adev->class == ATA_DEV_ATAPI) {
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struct mv_host_priv *hpriv = adev->link->ap->host->private_data;
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if (!IS_GEN_II(hpriv)) {
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xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
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ata_dev_printk(adev, KERN_INFO,
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"ATAPI DMA not supported on this chipset\n");
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}
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}
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return xfer_mask;
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}
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/**
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* mv_sff_irq_clear - Clear hardware interrupt after DMA.
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* @ap: Port associated with this ATA transaction.
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*
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* We need this only for ATAPI bmdma transactions,
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* as otherwise we experience spurious interrupts
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* after libata-sff handles the bmdma interrupts.
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*/
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static void mv_sff_irq_clear(struct ata_port *ap)
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{
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mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
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}
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/**
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* mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
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* @qc: queued command to check for chipset/DMA compatibility.
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*
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* The bmdma engines cannot handle speculative data sizes
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* (bytecount under/over flow). So only allow DMA for
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* data transfer commands with known data sizes.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
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{
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struct scsi_cmnd *scmd = qc->scsicmd;
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if (scmd) {
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switch (scmd->cmnd[0]) {
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case READ_6:
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case READ_10:
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case READ_12:
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case WRITE_6:
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case WRITE_10:
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case WRITE_12:
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case GPCMD_READ_CD:
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case GPCMD_SEND_DVD_STRUCTURE:
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case GPCMD_SEND_CUE_SHEET:
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return 0; /* DMA is safe */
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}
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}
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return -EOPNOTSUPP; /* use PIO instead */
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}
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/**
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* mv_bmdma_setup - Set up BMDMA transaction
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* @qc: queued command to prepare DMA for.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static void mv_bmdma_setup(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *port_mmio = mv_ap_base(ap);
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struct mv_port_priv *pp = ap->private_data;
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mv_fill_sg(qc);
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/* clear all DMA cmd bits */
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writel(0, port_mmio + BMDMA_CMD_OFS);
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/* load PRD table addr. */
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writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
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port_mmio + BMDMA_PRD_HIGH_OFS);
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writelfl(pp->sg_tbl_dma[qc->tag],
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port_mmio + BMDMA_PRD_LOW_OFS);
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/* issue r/w command */
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ap->ops->sff_exec_command(ap, &qc->tf);
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}
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/**
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* mv_bmdma_start - Start a BMDMA transaction
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* @qc: queued command to start DMA on.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static void mv_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *port_mmio = mv_ap_base(ap);
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
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/* start host DMA transaction */
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writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
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}
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/**
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* mv_bmdma_stop - Stop BMDMA transfer
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* @qc: queued command to stop DMA on.
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*
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* Clears the ATA_DMA_START flag in the bmdma control register
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static void mv_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *port_mmio = mv_ap_base(ap);
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u32 cmd;
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/* clear start/stop bit */
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cmd = readl(port_mmio + BMDMA_CMD_OFS);
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cmd &= ~ATA_DMA_START;
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writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
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/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
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ata_sff_dma_pause(ap);
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}
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/**
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* mv_bmdma_status - Read BMDMA status
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* @ap: port for which to retrieve DMA status.
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*
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* Read and return equivalent of the sff BMDMA status register.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static u8 mv_bmdma_status(struct ata_port *ap)
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{
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void __iomem *port_mmio = mv_ap_base(ap);
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u32 reg, status;
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/*
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* Other bits are valid only if ATA_DMA_ACTIVE==0,
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* and the ATA_DMA_INTR bit doesn't exist.
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*/
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reg = readl(port_mmio + BMDMA_STATUS_OFS);
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if (reg & ATA_DMA_ACTIVE)
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status = ATA_DMA_ACTIVE;
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else
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status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
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return status;
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}
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/**
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* mv_qc_prep - Host specific command preparation.
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* @qc: queued command to prepare
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