serial: sh-sci: Constify platform data
The driver modifies platform data for internal purpose only. Fix that and make the platform data structure const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -114,7 +114,7 @@ struct sci_port {
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/* Platform configuration */
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const struct sci_port_params *params;
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struct plat_sci_port *cfg;
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const struct plat_sci_port *cfg;
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unsigned int overrun_reg;
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unsigned int overrun_mask;
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unsigned int error_mask;
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@ -420,41 +420,6 @@ static void sci_serial_out(struct uart_port *p, int offset, int value)
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WARN(1, "Invalid register access\n");
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}
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static int sci_probe_regmap(struct plat_sci_port *cfg)
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{
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switch (cfg->type) {
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case PORT_SCI:
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cfg->regtype = SCIx_SCI_REGTYPE;
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break;
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case PORT_IRDA:
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cfg->regtype = SCIx_IRDA_REGTYPE;
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break;
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case PORT_SCIFA:
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cfg->regtype = SCIx_SCIFA_REGTYPE;
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break;
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case PORT_SCIFB:
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cfg->regtype = SCIx_SCIFB_REGTYPE;
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break;
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case PORT_SCIF:
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/*
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* The SH-4 is a bit of a misnomer here, although that's
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* where this particular port layout originated. This
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* configuration (or some slight variation thereof)
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* remains the dominant model for all SCIFs.
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*/
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cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
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break;
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case PORT_HSCIF:
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cfg->regtype = SCIx_HSCIF_REGTYPE;
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break;
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default:
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pr_err("Can't probe register map for given port\n");
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return -EINVAL;
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}
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return 0;
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}
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static void sci_port_enable(struct sci_port *sci_port)
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{
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unsigned int i;
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@ -2541,9 +2506,50 @@ found:
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return 0;
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}
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static const struct sci_port_params *
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sci_probe_regmap(const struct plat_sci_port *cfg)
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{
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unsigned int regtype;
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if (cfg->regtype != SCIx_PROBE_REGTYPE)
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return &sci_port_params[cfg->regtype];
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switch (cfg->type) {
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case PORT_SCI:
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regtype = SCIx_SCI_REGTYPE;
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break;
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case PORT_IRDA:
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regtype = SCIx_IRDA_REGTYPE;
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break;
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case PORT_SCIFA:
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regtype = SCIx_SCIFA_REGTYPE;
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break;
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case PORT_SCIFB:
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regtype = SCIx_SCIFB_REGTYPE;
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break;
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case PORT_SCIF:
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/*
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* The SH-4 is a bit of a misnomer here, although that's
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* where this particular port layout originated. This
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* configuration (or some slight variation thereof)
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* remains the dominant model for all SCIFs.
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*/
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regtype = SCIx_SH4_SCIF_REGTYPE;
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break;
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case PORT_HSCIF:
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regtype = SCIx_HSCIF_REGTYPE;
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break;
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default:
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pr_err("Can't probe register map for given port\n");
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return NULL;
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}
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return &sci_port_params[regtype];
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}
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static int sci_init_single(struct platform_device *dev,
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struct sci_port *sci_port, unsigned int index,
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struct plat_sci_port *p, bool early)
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const struct plat_sci_port *p, bool early)
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{
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struct uart_port *port = &sci_port->port;
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const struct resource *res;
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@ -2580,13 +2586,9 @@ static int sci_init_single(struct platform_device *dev,
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sci_port->irqs[3] = sci_port->irqs[0];
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}
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if (p->regtype == SCIx_PROBE_REGTYPE) {
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ret = sci_probe_regmap(p);
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if (unlikely(ret))
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return ret;
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}
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sci_port->params = &sci_port_params[p->regtype];
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sci_port->params = sci_probe_regmap(p);
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if (unlikely(sci_port->params == NULL))
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return -EINVAL;
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switch (p->type) {
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case PORT_SCIFB:
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@ -2806,7 +2808,7 @@ static char early_serial_buf[32];
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static int sci_probe_earlyprintk(struct platform_device *pdev)
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{
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struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
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const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
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if (early_serial_console.data)
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return -EEXIST;
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@ -3097,10 +3099,9 @@ static int __init early_console_setup(struct earlycon_device *device,
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device->port.serial_out = sci_serial_out;
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device->port.type = type;
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memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
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port_cfg.type = type;
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sci_ports[0].cfg = &port_cfg;
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sci_ports[0].cfg->type = type;
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sci_probe_regmap(sci_ports[0].cfg);
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sci_ports[0].params = &sci_port_params[sci_ports[0].cfg->regtype];
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sci_ports[0].params = sci_probe_regmap(&port_cfg);
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port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
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sci_serial_out(&sci_ports[0].port, SCSCR,
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SCSCR_RE | SCSCR_TE | port_cfg.scscr);
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