From db4cea918e11d1cd1cb870049b2af17fe99d7b94 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 23 Aug 2018 13:44:20 +0900 Subject: [PATCH] mmc: tmio: refactor CLK_CTL bit calculation for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) clock <<= 1; ... is too tricky, hence I replaced with roundup_pow_of_two(divisor) >> 2 '(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but it is not clear. 'divisor <= 1' is easier to understand. Signed-off-by: Masahiro Yamada Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Signed-off-by: Ulf Hansson --- drivers/mmc/host/tmio_mmc.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index 09bb104e3fff..0ae9ba1ee01b 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -45,19 +45,27 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) static void tmio_mmc_set_clock(struct tmio_mmc_host *host, unsigned int new_clock) { - u32 clk = 0, clock; + unsigned int clock, divisor; + u32 clk = 0; + int clk_sel; if (new_clock == 0) { tmio_mmc_clk_stop(host); return; } - clock = host->mmc->f_min; + divisor = host->pdata->hclk / new_clock; - for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) - clock <<= 1; + if (divisor <= 1) { + clk_sel = 1; + clk = 0; + } else { + clk_sel = 0; + /* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */ + clk = roundup_pow_of_two(divisor) >> 2; + } - host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1); + host->pdata->set_clk_div(host->pdev, clk_sel); sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));