omap: gpmc: enable irq mode in gpmc
add support the irq mode in GPMC. gpmc_init() function move after omap_init_irq() as it has dependecy on irq. Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>hifive-unleashed-5.1
Sukumar Ghorai
Tony Lindgren
parent
1b0b323c70
commit
db97eb7dfe
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@ -14,6 +14,7 @@
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*/
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#undef DEBUG
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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@ -22,6 +23,7 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <asm/mach-types.h>
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#include <plat/gpmc.h>
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@ -100,6 +102,8 @@ static void __iomem *gpmc_base;
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static struct clk *gpmc_l3_clk;
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static irqreturn_t gpmc_handle_irq(int irq, void *dev);
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static void gpmc_write_reg(int idx, u32 val)
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{
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__raw_writel(val, gpmc_base + idx);
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@ -497,6 +501,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
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u32 regval = 0;
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switch (cmd) {
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case GPMC_ENABLE_IRQ:
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gpmc_write_reg(GPMC_IRQENABLE, wval);
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break;
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case GPMC_SET_IRQ_STATUS:
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gpmc_write_reg(GPMC_IRQSTATUS, wval);
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break;
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@ -678,9 +686,10 @@ static void __init gpmc_mem_init(void)
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}
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}
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void __init gpmc_init(void)
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static int __init gpmc_init(void)
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{
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u32 l;
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u32 l, irq;
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int cs, ret = -EINVAL;
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char *ck = NULL;
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if (cpu_is_omap24xx()) {
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@ -698,7 +707,7 @@ void __init gpmc_init(void)
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}
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if (WARN_ON(!ck))
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return;
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return ret;
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gpmc_l3_clk = clk_get(NULL, ck);
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if (IS_ERR(gpmc_l3_clk)) {
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@ -723,6 +732,36 @@ void __init gpmc_init(void)
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l |= (0x02 << 3) | (1 << 0);
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gpmc_write_reg(GPMC_SYSCONFIG, l);
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gpmc_mem_init();
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/* initalize the irq_chained */
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irq = OMAP_GPMC_IRQ_BASE;
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for (cs = 0; cs < GPMC_CS_NUM; cs++) {
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set_irq_handler(irq, handle_simple_irq);
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set_irq_flags(irq, IRQF_VALID);
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irq++;
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}
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ret = request_irq(INT_34XX_GPMC_IRQ,
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gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
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if (ret)
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pr_err("gpmc: irq-%d could not claim: err %d\n",
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INT_34XX_GPMC_IRQ, ret);
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return ret;
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}
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postcore_initcall(gpmc_init);
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static irqreturn_t gpmc_handle_irq(int irq, void *dev)
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{
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u8 cs;
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if (irq != INT_34XX_GPMC_IRQ)
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return IRQ_HANDLED;
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/* check cs to invoke the irq */
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cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
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if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
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generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_ARCH_OMAP3
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@ -30,7 +30,6 @@
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#include <plat/sram.h>
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#include <plat/sdrc.h>
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#include <plat/gpmc.h>
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#include <plat/serial.h>
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#include "clock2xxx.h"
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@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
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omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
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_omap2_init_reprogram_sdrc();
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}
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gpmc_init();
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omap_irq_base_init();
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}
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@ -41,6 +41,8 @@
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#define GPMC_NAND_ADDRESS 0x0000000b
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#define GPMC_NAND_DATA 0x0000000c
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#define GPMC_ENABLE_IRQ 0x0000000d
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/* ECC commands */
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#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
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#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
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@ -78,6 +80,8 @@
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#define WR_RD_PIN_MONITORING 0x00600000
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#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
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#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
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#define GPMC_IRQ_FIFOEVENTENABLE 0x01
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#define GPMC_IRQ_COUNT_EVENT 0x02
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/*
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* Note that all values in this struct are in nanoseconds except sync_clk
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@ -135,7 +139,6 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode,
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extern int gpmc_prefetch_reset(int cs);
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extern void omap3_gpmc_save_context(void);
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extern void omap3_gpmc_restore_context(void);
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extern void gpmc_init(void);
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extern int gpmc_read_status(int cmd);
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extern int gpmc_cs_configure(int cs, int cmd, int wval);
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extern int gpmc_nand_read(int cs, int cmd);
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@ -318,6 +318,7 @@
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#define INT_34XX_PRCM_MPU_IRQ 11
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#define INT_34XX_MCBSP1_IRQ 16
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#define INT_34XX_MCBSP2_IRQ 17
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#define INT_34XX_GPMC_IRQ 20
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#define INT_34XX_MCBSP3_IRQ 22
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#define INT_34XX_MCBSP4_IRQ 23
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#define INT_34XX_CAM_IRQ 24
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@ -411,7 +412,13 @@
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#define TWL_IRQ_END TWL6030_IRQ_END
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#endif
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#define NR_IRQS TWL_IRQ_END
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/* GPMC related */
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#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
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#define OMAP_GPMC_NR_IRQS 7
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#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
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#define NR_IRQS OMAP_GPMC_IRQ_END
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#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
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