redonkable/alistair23-linux
redonkable/alistair23-linux
1
0
Fork 0
Code Releases Activity

V4L/DVB (7568): Support for DVB-S demod PN1010 (clone of S5H1420) added

Browse source 
This device is a clone of the PN1010 used by SkyStar2 rev2.7 .

This patch adds support for the flexcop-device and makes the driver look a little bit nicer.

It needs to be checked whether the driver is still ok for the budget-cards.

Signed-off-by: Patrick Boettcher <pb@linuxtv.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Patrick Boettcher 2008-04-13 15:47:53 -03:00 committed by Mauro Carvalho Chehab
parent 44dc733cd9
commit dbad108bdc
4 changed files with 470 additions and 214 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

519
drivers/media/dvb/frontends/s5h1420.c
View file

@ -1,24 +1,26 @@
/*
Driver for Samsung S5H1420 QPSK Demodulator
Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
* Driver for
* Samsung S5H1420 and
* PnpNetwork PN1010 QPSK Demodulator
*
* Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
* Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/module.h>
@ -29,23 +31,35 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#include <linux/jiffies.h>
#include <asm/div64.h>
#include <linux/i2c.h>
#include "dvb_frontend.h"
#include "s5h1420.h"
#include "s5h1420_priv.h"
#define TONE_FREQ 22000
struct s5h1420_state {
struct i2c_adapter* i2c;
const struct s5h1420_config* config;
struct dvb_frontend frontend;
struct i2c_adapter tuner_i2c_adapter;
u8 CON_1_val;
u8 postlocked:1;
u32 fclk;
u32 tunedfreq;
fe_code_rate_t fec_inner;
u32 symbol_rate;
/* FIXME: ugly workaround for flexcop's incapable i2c-controller
* it does not support repeated-start, workaround: write addr-1
* and then read
*/
u8 shadow[255];
};
static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
@ -54,43 +68,65 @@ static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
static int debug;
#define dprintk if (debug) printk
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debugging");
#define dprintk(x...) do { \
if (debug) \
printk(KERN_DEBUG "S5H1420: " x); \
} while (0)
static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
{
int ret;
u8 b[2];
struct i2c_msg msg[] = {
{ .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
{ .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 },
{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
};
b[0] = (reg - 1) & 0xff;
b[1] = state->shadow[(reg - 1) & 0xff];
if (state->config->repeated_start_workaround) {
ret = i2c_transfer(state->i2c, msg, 3);
if (ret != 3)
return ret;
} else {
ret = i2c_transfer(state->i2c, &msg[1], 2);
if (ret != 2)
return ret;
}
/* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
return b[0];
}
static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
{
u8 buf [] = { reg, data };
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
int err;
if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
/* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
err = i2c_transfer(state->i2c, &msg, 1);
if (err != 1) {
dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
return -EREMOTEIO;
}
state->shadow[reg] = data;
return 0;
}
static u8 s5h1420_readreg (struct s5h1420_state* state, u8 reg)
{
int ret;
u8 b0 [] = { reg };
u8 b1 [] = { 0 };
struct i2c_msg msg1 = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 };
struct i2c_msg msg2 = { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 };
if ((ret = i2c_transfer (state->i2c, &msg1, 1)) != 1)
return ret;
if ((ret = i2c_transfer (state->i2c, &msg2, 1)) != 1)
return ret;
return b1[0];
}
static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
{
struct s5h1420_state* state = fe->demodulator_priv;
dprintk("enter %s\n", __func__);
switch(voltage) {
case SEC_VOLTAGE_13:
s5h1420_writereg(state, 0x3c,
@ -106,6 +142,7 @@ static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltag
break;
}
dprintk("leave %s\n", __func__);
return 0;
}
@ -113,6 +150,7 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
{
struct s5h1420_state* state = fe->demodulator_priv;
dprintk("enter %s\n", __func__);
switch(tone) {
case SEC_TONE_ON:
s5h1420_writereg(state, 0x3b,
@ -124,6 +162,7 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
(s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
break;
}
dprintk("leave %s\n", __func__);
return 0;
}
@ -137,6 +176,7 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
unsigned long timeout;
int result = 0;
dprintk("enter %s\n", __func__);
if (cmd->msg_len > 8)
return -EINVAL;
@ -168,6 +208,7 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
/* restore original settings */
s5h1420_writereg(state, 0x3b, val);
msleep(15);
dprintk("leave %s\n", __func__);
return result;
}
@ -289,6 +330,8 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
struct s5h1420_state* state = fe->demodulator_priv;
u8 val;
dprintk("enter %s\n", __func__);
if (status == NULL)
return -EINVAL;
@ -297,13 +340,13 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
the inversion, wait a bit and check again */
if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) {
val = s5h1420_readreg(state, 0x32);
if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
val = s5h1420_readreg(state, Vit10);
if ((val & 0x07) == 0x03) {
if (val & 0x08)
s5h1420_writereg(state, 0x31, 0x13);
s5h1420_writereg(state, Vit09, 0x13);
else
s5h1420_writereg(state, 0x31, 0x1b);
s5h1420_writereg(state, Vit09, 0x1b);
/* wait a bit then update lock status */
mdelay(200);
@ -312,68 +355,73 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
}
/* perform post lock setup */
if ((*status & FE_HAS_LOCK) && (!state->postlocked)) {
if ((*status & FE_HAS_LOCK) && !state->postlocked) {
/* calculate the data rate */
u32 tmp = s5h1420_getsymbolrate(state);
switch(s5h1420_readreg(state, 0x32) & 0x07) {
case 0:
tmp = (tmp * 2 * 1) / 2;
break;
case 1:
tmp = (tmp * 2 * 2) / 3;
break;
case 2:
tmp = (tmp * 2 * 3) / 4;
break;
case 3:
tmp = (tmp * 2 * 5) / 6;
break;
case 4:
tmp = (tmp * 2 * 6) / 7;
break;
case 5:
tmp = (tmp * 2 * 7) / 8;
break;
switch (s5h1420_readreg(state, Vit10) & 0x07) {
case 0: tmp = (tmp * 2 * 1) / 2; break;
case 1: tmp = (tmp * 2 * 2) / 3; break;
case 2: tmp = (tmp * 2 * 3) / 4; break;
case 3: tmp = (tmp * 2 * 5) / 6; break;
case 4: tmp = (tmp * 2 * 6) / 7; break;
case 5: tmp = (tmp * 2 * 7) / 8; break;
}
if (tmp == 0) {
printk("s5h1420: avoided division by 0\n");
printk(KERN_ERR "s5h1420: avoided division by 0\n");
tmp = 1;
}
tmp = state->fclk / tmp;
/* set the MPEG_CLK_INTL for the calculated data rate */
if (tmp < 4)
if (tmp < 2)
val = 0x00;
else if (tmp < 8)
else if (tmp < 5)
val = 0x01;
else if (tmp < 12)
else if (tmp < 9)
val = 0x02;
else if (tmp < 16)
else if (tmp < 13)
val = 0x03;
else if (tmp < 24)
else if (tmp < 17)
val = 0x04;
else if (tmp < 32)
else if (tmp < 25)
val = 0x05;
else
else if (tmp < 33)
val = 0x06;
s5h1420_writereg(state, 0x22, val);
else
val = 0x07;
dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
/* DC freeze */
s5h1420_writereg(state, 0x1f, s5h1420_readreg(state, 0x1f) | 0x01);
s5h1420_writereg(state, FEC01, 0x18);
s5h1420_writereg(state, FEC01, 0x10);
s5h1420_writereg(state, FEC01, val);
/* kicker disable + remove DC offset */
s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) & 0x6f);
/* Enable "MPEG_Out" */
val = s5h1420_readreg(state, Mpeg02);
s5h1420_writereg(state, Mpeg02, val | (1 << 6));
/* kicker disable */
val = s5h1420_readreg(state, QPSK01) & 0x7f;
s5h1420_writereg(state, QPSK01, val);
/* DC freeze TODO it was never activated by default or it can stay activated */
if (s5h1420_getsymbolrate(state) >= 20000000) {
s5h1420_writereg(state, Loop04, 0x8a);
s5h1420_writereg(state, Loop05, 0x6a);
} else {
s5h1420_writereg(state, Loop04, 0x58);
s5h1420_writereg(state, Loop05, 0x27);
}
/* post-lock processing has been done! */
state->postlocked = 1;
}
dprintk("leave %s\n", __func__);
return 0;
}
@ -414,6 +462,7 @@ static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
static void s5h1420_reset(struct s5h1420_state* state)
{
dprintk("%s\n", __func__);
s5h1420_writereg (state, 0x01, 0x08);
s5h1420_writereg (state, 0x01, 0x00);
udelay(10);
@ -422,54 +471,52 @@ static void s5h1420_reset(struct s5h1420_state* state)
static void s5h1420_setsymbolrate(struct s5h1420_state* state,
struct dvb_frontend_parameters *p)
{
u8 v;
u64 val;
dprintk("enter %s\n", __func__);
val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
if (p->u.qpsk.symbol_rate <= 21000000) {
if (p->u.qpsk.symbol_rate < 29000000)
val *= 2;
}
do_div(val, (state->fclk / 1000));
s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0x7f);
s5h1420_writereg(state, 0x11, val >> 16);
s5h1420_writereg(state, 0x12, val >> 8);
s5h1420_writereg(state, 0x13, val & 0xff);
s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x80);
dprintk("symbol rate register: %06llx\n", val);
v = s5h1420_readreg(state, Loop01);
s5h1420_writereg(state, Loop01, v & 0x7f);
s5h1420_writereg(state, Tnco01, val >> 16);
s5h1420_writereg(state, Tnco02, val >> 8);
s5h1420_writereg(state, Tnco03, val & 0xff);
s5h1420_writereg(state, Loop01, v | 0x80);
dprintk("leave %s\n", __func__);
}
static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
{
u64 val = 0;
int sampling = 2;
if (s5h1420_readreg(state, 0x05) & 0x2)
sampling = 1;
s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
val = s5h1420_readreg(state, 0x11) << 16;
val |= s5h1420_readreg(state, 0x12) << 8;
val |= s5h1420_readreg(state, 0x13);
s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
val *= (state->fclk / 1000ULL);
do_div(val, ((1<<24) * sampling));
return (u32) (val * 1000ULL);
return state->symbol_rate;
}
static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
{
int val;
u8 v;
dprintk("enter %s\n", __func__);
/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
* divide fclk by 1000000 to get the correct value. */
val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0xbf);
s5h1420_writereg(state, 0x0e, val >> 16);
s5h1420_writereg(state, 0x0f, val >> 8);
s5h1420_writereg(state, 0x10, val & 0xff);
s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x40);
dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
v = s5h1420_readreg(state, Loop01);
s5h1420_writereg(state, Loop01, v & 0xbf);
s5h1420_writereg(state, Pnco01, val >> 16);
s5h1420_writereg(state, Pnco02, val >> 8);
s5h1420_writereg(state, Pnco03, val & 0xff);
s5h1420_writereg(state, Loop01, v | 0x40);
dprintk("leave %s\n", __func__);
}
static int s5h1420_getfreqoffset(struct s5h1420_state* state)
@ -496,52 +543,53 @@ static void s5h1420_setfec_inversion(struct s5h1420_state* state,
struct dvb_frontend_parameters *p)
{
u8 inversion = 0;
u8 vit08, vit09;
if (p->inversion == INVERSION_OFF) {
dprintk("enter %s\n", __func__);
if (p->inversion == INVERSION_OFF)
inversion = state->config->invert ? 0x08 : 0;
} else if (p->inversion == INVERSION_ON) {
else if (p->inversion == INVERSION_ON)
inversion = state->config->invert ? 0 : 0x08;
}
if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
s5h1420_writereg(state, 0x30, 0x3f);
s5h1420_writereg(state, 0x31, 0x00 | inversion);
vit08 = 0x3f;
vit09 = 0;
} else {
switch(p->u.qpsk.fec_inner) {
case FEC_1_2:
s5h1420_writereg(state, 0x30, 0x01);
s5h1420_writereg(state, 0x31, 0x10 | inversion);
vit08 = 0x01; vit09 = 0x10;
break;
case FEC_2_3:
s5h1420_writereg(state, 0x30, 0x02);
s5h1420_writereg(state, 0x31, 0x11 | inversion);
vit08 = 0x02; vit09 = 0x11;
break;
case FEC_3_4:
s5h1420_writereg(state, 0x30, 0x04);
s5h1420_writereg(state, 0x31, 0x12 | inversion);
vit08 = 0x04; vit09 = 0x12;
break;
case FEC_5_6:
s5h1420_writereg(state, 0x30, 0x08);
s5h1420_writereg(state, 0x31, 0x13 | inversion);
vit08 = 0x08; vit09 = 0x13;
break;
case FEC_6_7:
s5h1420_writereg(state, 0x30, 0x10);
s5h1420_writereg(state, 0x31, 0x14 | inversion);
vit08 = 0x10; vit09 = 0x14;
break;
case FEC_7_8:
s5h1420_writereg(state, 0x30, 0x20);
s5h1420_writereg(state, 0x31, 0x15 | inversion);
vit08 = 0x20; vit09 = 0x15;
break;
default:
return;
}
}
vit09 |= inversion;
dprintk("fec: %02x %02x\n", vit08, vit09);
s5h1420_writereg(state, Vit08, vit08);
s5h1420_writereg(state, Vit09, vit09);
dprintk("leave %s\n", __func__);
}
static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
@ -583,16 +631,19 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
struct s5h1420_state* state = fe->demodulator_priv;
int frequency_delta;
struct dvb_frontend_tune_settings fesettings;
uint8_t clock_settting;
dprintk("enter %s\n", __func__);
/* check if we should do a fast-tune */
memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
s5h1420_get_tune_settings(fe, &fesettings);
frequency_delta = p->frequency - state->tunedfreq;
if ((frequency_delta > -fesettings.max_drift) &&
(frequency_delta < fesettings.max_drift) &&
(frequency_delta != 0) &&
(state->fec_inner == p->u.qpsk.fec_inner) &&
(state->symbol_rate == p->u.qpsk.symbol_rate)) {
(frequency_delta < fesettings.max_drift) &&
(frequency_delta != 0) &&
(state->fec_inner == p->u.qpsk.fec_inner) &&
(state->symbol_rate == p->u.qpsk.symbol_rate)) {
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe, p);
@ -606,54 +657,93 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
} else {
s5h1420_setfreqoffset(state, 0);
}
dprintk("simple tune\n");
return 0;
}
dprintk("tuning demod\n");
/* first of all, software reset */
s5h1420_reset(state);
/* set s5h1420 fclk PLL according to desired symbol rate */
if (p->u.qpsk.symbol_rate > 28000000) {
state->fclk = 88000000;
s5h1420_writereg(state, 0x03, 0x50);
s5h1420_writereg(state, 0x04, 0x40);
s5h1420_writereg(state, 0x05, 0xae);
} else if (p->u.qpsk.symbol_rate > 21000000) {
if (p->u.qpsk.symbol_rate > 33000000)
state->fclk = 80000000;
else if (p->u.qpsk.symbol_rate > 28500000)
state->fclk = 59000000;
s5h1420_writereg(state, 0x03, 0x33);
s5h1420_writereg(state, 0x04, 0x40);
s5h1420_writereg(state, 0x05, 0xae);
} else {
else if (p->u.qpsk.symbol_rate > 25000000)
state->fclk = 86000000;
else if (p->u.qpsk.symbol_rate > 1900000)
state->fclk = 88000000;
s5h1420_writereg(state, 0x03, 0x50);
s5h1420_writereg(state, 0x04, 0x40);
s5h1420_writereg(state, 0x05, 0xac);
else
state->fclk = 44000000;
/* Clock */
switch (state->fclk) {
default:
case 88000000:
clock_settting = 80;
break;
case 86000000:
clock_settting = 78;
break;
case 80000000:
clock_settting = 72;
break;
case 59000000:
clock_settting = 51;
break;
case 44000000:
clock_settting = 36;
break;
}
dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
s5h1420_writereg(state, PLL02, 0x40);
s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
/* TODO DC offset removal, config parameter ? */
if (p->u.qpsk.symbol_rate > 29000000)
s5h1420_writereg(state, QPSK01, 0xae | 0x10);
else
s5h1420_writereg(state, QPSK01, 0xac | 0x10);
/* set misc registers */
s5h1420_writereg(state, 0x02, 0x00);
s5h1420_writereg(state, 0x06, 0x00);
s5h1420_writereg(state, 0x07, 0xb0);
s5h1420_writereg(state, 0x0a, 0xe7);
s5h1420_writereg(state, 0x0b, 0x78);
s5h1420_writereg(state, 0x0c, 0x48);
s5h1420_writereg(state, 0x0d, 0x6b);
s5h1420_writereg(state, 0x2e, 0x8e);
s5h1420_writereg(state, 0x35, 0x33);
s5h1420_writereg(state, 0x38, 0x01);
s5h1420_writereg(state, 0x39, 0x7d);
s5h1420_writereg(state, 0x3a, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
s5h1420_writereg(state, 0x3c, 0x00);
s5h1420_writereg(state, 0x45, 0x61);
s5h1420_writereg(state, 0x46, 0x1d);
s5h1420_writereg(state, CON_1, 0x00);
s5h1420_writereg(state, QPSK02, 0x00);
s5h1420_writereg(state, Pre01, 0xb0);
/* start QPSK */
s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1);
s5h1420_writereg(state, Loop01, 0xF0);
s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
if (p->u.qpsk.symbol_rate > 20000000)
s5h1420_writereg(state, Loop04, 0x79);
else
s5h1420_writereg(state, Loop04, 0x58);
s5h1420_writereg(state, Loop05, 0x6b);
if (p->u.qpsk.symbol_rate >= 8000000)
s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
else if (p->u.qpsk.symbol_rate >= 4000000)
s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
else
s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
s5h1420_writereg(state, Sync01, 0x33);
s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
s5h1420_writereg(state, DiS03, 0x00);
s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
/* set tuner PLL */
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe, p);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
s5h1420_setfreqoffset(state, 0);
}
@ -661,10 +751,15 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
s5h1420_setsymbolrate(state, p);
s5h1420_setfec_inversion(state, p);
/* start QPSK */
s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
state->fec_inner = p->u.qpsk.fec_inner;
state->symbol_rate = p->u.qpsk.symbol_rate;
state->postlocked = 0;
state->tunedfreq = p->frequency;
dprintk("leave %s\n", __func__);
return 0;
}
@ -717,11 +812,10 @@ static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct s5h1420_state* state = fe->demodulator_priv;
if (enable) {
return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
} else {
return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe);
}
if (enable)
return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
else
return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
}
static int s5h1420_init (struct dvb_frontend* fe)
@ -729,7 +823,8 @@ static int s5h1420_init (struct dvb_frontend* fe)
struct s5h1420_state* state = fe->demodulator_priv;
/* disable power down and do reset */
s5h1420_writereg(state, 0x02, 0x10);
state->CON_1_val = 0x10;
s5h1420_writereg(state, 0x02, state->CON_1_val);
msleep(10);
s5h1420_reset(state);
@ -739,26 +834,60 @@ static int s5h1420_init (struct dvb_frontend* fe)
static int s5h1420_sleep(struct dvb_frontend* fe)
{
struct s5h1420_state* state = fe->demodulator_priv;
return s5h1420_writereg(state, 0x02, 0x12);
state->CON_1_val = 0x12;
return s5h1420_writereg(state, 0x02, state->CON_1_val);
}
static void s5h1420_release(struct dvb_frontend* fe)
{
struct s5h1420_state* state = fe->demodulator_priv;
i2c_del_adapter(&state->tuner_i2c_adapter);
kfree(state);
}
static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
struct i2c_msg m[1 + num];
u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
m[0].addr = state->config->demod_address;
m[0].buf = tx_open;
m[0].len = 2;
memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
return i2c_transfer(state->i2c, m, 1+num) == 1 + num ? num : -EIO;
}
static struct i2c_algorithm s5h1420_tuner_i2c_algo = {
.master_xfer = s5h1420_tuner_i2c_tuner_xfer,
.functionality = s5h1420_tuner_i2c_func,
};
struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
{
struct s5h1420_state *state = fe->demodulator_priv;
return &state->tuner_i2c_adapter;
}
EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
static struct dvb_frontend_ops s5h1420_ops;
struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
struct i2c_adapter* i2c)
struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
struct i2c_adapter *i2c)
{
struct s5h1420_state* state = NULL;
u8 identity;
/* allocate memory for the internal state */
state = kmalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
u8 i;
if (state == NULL)
goto error;
@ -772,24 +901,42 @@ struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
state->symbol_rate = 0;
/* check if the demod is there + identify it */
identity = s5h1420_readreg(state, 0x00);
if (identity != 0x03)
i = s5h1420_readreg(state, ID01);
if (i != 0x03)
goto error;
memset(state->shadow, 0xff, sizeof(state->shadow));
for (i = 0; i < 0x50; i++)
state->shadow[i] = s5h1420_readreg(state, i);
/* create dvb_frontend */
memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* create tuner i2c adapter */
strncpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus", I2C_NAME_SIZE);
state->tuner_i2c_adapter.class = I2C_CLASS_TV_DIGITAL,
state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
state->tuner_i2c_adapter.algo_data = NULL;
i2c_set_adapdata(&state->tuner_i2c_adapter, state);
if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
goto error;
}
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL(s5h1420_attach);
static struct dvb_frontend_ops s5h1420_ops = {
.info = {
.name = "Samsung S5H1420 DVB-S",
.name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
.type = FE_QPSK,
.frequency_min = 950000,
.frequency_max = 2150000,
@ -826,10 +973,6 @@ static struct dvb_frontend_ops s5h1420_ops = {
.set_voltage = s5h1420_set_voltage,
};
module_param(debug, int, 0644);
MODULE_DESCRIPTION("Samsung S5H1420 DVB-S Demodulator driver");
MODULE_AUTHOR("Andrew de Quincey");
MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL(s5h1420_attach);

62
drivers/media/dvb/frontends/s5h1420.h
View file

@ -1,25 +1,26 @@
/*
Driver for S5H1420 QPSK Demodulators
Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
* Driver for
* Samsung S5H1420 and
* PnpNetwork PN1010 QPSK Demodulator
*
* Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
* Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef S5H1420_H
#define S5H1420_H
@ -31,19 +32,28 @@ struct s5h1420_config
u8 demod_address;
/* does the inversion require inversion? */
u8 invert:1;
u8 invert : 1;
u8 repeated_start_workaround : 1;
u8 cdclk_polarity : 1; /* 1 == falling edge, 0 == raising edge */
};
#if defined(CONFIG_DVB_S5H1420) || (defined(CONFIG_DVB_S5H1420_MODULE) && defined(MODULE))
extern struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
struct i2c_adapter* i2c);
extern struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
struct i2c_adapter *i2c);
extern struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe);
#else
static inline struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
struct i2c_adapter* i2c)
static inline struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
struct i2c_adapter *i2c)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
static inline struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
{
return NULL;
}
#endif // CONFIG_DVB_S5H1420
#endif // S5H1420_H

102
drivers/media/dvb/frontends/s5h1420_priv.h Normal file
View file

@ -0,0 +1,102 @@
/*
* Driver for
* Samsung S5H1420 and
* PnpNetwork PN1010 QPSK Demodulator
*
* Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
* Copyright (C) 2005 Patrick Boettcher <pb@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 675 Mass
* Ave, Cambridge, MA 02139, USA.
*/
#ifndef S5H1420_PRIV
#define S5H1420_PRIV
#include <asm/types.h>
enum s5h1420_register {
ID01 = 0x00,
CON_0 = 0x01,
CON_1 = 0x02,
PLL01 = 0x03,
PLL02 = 0x04,
QPSK01 = 0x05,
QPSK02 = 0x06,
Pre01 = 0x07,
Post01 = 0x08,
Loop01 = 0x09,
Loop02 = 0x0a,
Loop03 = 0x0b,
Loop04 = 0x0c,
Loop05 = 0x0d,
Pnco01 = 0x0e,
Pnco02 = 0x0f,
Pnco03 = 0x10,
Tnco01 = 0x11,
Tnco02 = 0x12,
Tnco03 = 0x13,
Monitor01 = 0x14,
Monitor02 = 0x15,
Monitor03 = 0x16,
Monitor04 = 0x17,
Monitor05 = 0x18,
Monitor06 = 0x19,
Monitor07 = 0x1a,
Monitor12 = 0x1f,
FEC01 = 0x22,
Soft01 = 0x23,
Soft02 = 0x24,
Soft03 = 0x25,
Soft04 = 0x26,
Soft05 = 0x27,
Soft06 = 0x28,
Vit01 = 0x29,
Vit02 = 0x2a,
Vit03 = 0x2b,
Vit04 = 0x2c,
Vit05 = 0x2d,
Vit06 = 0x2e,
Vit07 = 0x2f,
Vit08 = 0x30,
Vit09 = 0x31,
Vit10 = 0x32,
Vit11 = 0x33,
Vit12 = 0x34,
Sync01 = 0x35,
Sync02 = 0x36,
Rs01 = 0x37,
Mpeg01 = 0x38,
Mpeg02 = 0x39,
DiS01 = 0x3a,
DiS02 = 0x3b,
DiS03 = 0x3c,
DiS04 = 0x3d,
DiS05 = 0x3e,
DiS06 = 0x3f,
DiS07 = 0x40,
DiS08 = 0x41,
DiS09 = 0x42,
DiS10 = 0x43,
DiS11 = 0x44,
Rf01 = 0x45,
Err01 = 0x46,
Err02 = 0x47,
Err03 = 0x48,
Err04 = 0x49,
};
#endif

1
drivers/media/dvb/ttpci/budget.c
View file

@ -358,6 +358,7 @@ static int s5h1420_tuner_set_params(struct dvb_frontend* fe, struct dvb_frontend
static struct s5h1420_config s5h1420_config = {
.demod_address = 0x53,
.invert = 1,
.cdclk_polarity = 1,
};
static struct tda10086_config tda10086_config = {