net: aquantia: add support for Phy access
GPIO PIN control and access is done by direct phy manipulation. Here we add an aq_phy module which is able to access phy registers via MDIO access mailbox. Access is controlled via HW semaphore. Co-developed-by: Nikita Danilov <nikita.danilov@aquantia.com> Signed-off-by: Nikita Danilov <nikita.danilov@aquantia.com> Signed-off-by: Dmitry Bezrukov <dmitry.bezrukov@aquantia.com> Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>alistair/sunxi64-5.5-dsi
Dmitry Bezrukov
David S. Miller
parent
84989af046
commit
dbcd6806af
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@ -25,6 +25,7 @@ atlantic-objs := aq_main.o \
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aq_drvinfo.o \
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aq_filters.o \
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aq_ptp.o \
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aq_phy.o \
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hw_atl/hw_atl_a0.o \
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hw_atl/hw_atl_b0.o \
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hw_atl/hw_atl_utils.o \
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@ -140,6 +140,7 @@ struct aq_hw_s {
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u32 rpc_tid;
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struct hw_atl_utils_fw_rpc rpc;
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s64 ptp_clk_offset;
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u16 phy_id;
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};
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struct aq_ring_s;
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@ -12,6 +12,7 @@
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#include "aq_hw.h"
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#include "aq_pci_func.h"
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#include "aq_main.h"
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#include "aq_phy.h"
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#include "aq_ptp.h"
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#include "aq_filters.h"
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@ -337,6 +338,11 @@ int aq_nic_init(struct aq_nic_s *self)
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if (err < 0)
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goto err_exit;
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if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_TP) {
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self->aq_hw->phy_id = HW_ATL_PHY_ID_MAX;
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err = aq_phy_init(self->aq_hw);
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}
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for (i = 0U, aq_vec = self->aq_vec[0];
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self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
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aq_vec_init(aq_vec, self->aq_hw_ops, self->aq_hw);
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@ -0,0 +1,147 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* aQuantia Corporation Network Driver
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* Copyright (C) 2018-2019 aQuantia Corporation. All rights reserved
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*/
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#include "aq_phy.h"
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bool aq_mdio_busy_wait(struct aq_hw_s *aq_hw)
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{
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int err = 0;
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u32 val;
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err = readx_poll_timeout_atomic(hw_atl_mdio_busy_get, aq_hw,
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val, val == 0U, 10U, 100000U);
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if (err < 0)
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return false;
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return true;
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}
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u16 aq_mdio_read_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr)
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{
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u16 phy_addr = aq_hw->phy_id << 5 | mmd;
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/* Set Address register. */
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hw_atl_glb_mdio_iface4_set(aq_hw, (addr & HW_ATL_MDIO_ADDRESS_MSK) <<
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HW_ATL_MDIO_ADDRESS_SHIFT);
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/* Send Address command. */
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hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
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(3 << HW_ATL_MDIO_OP_MODE_SHIFT) |
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((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
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HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
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aq_mdio_busy_wait(aq_hw);
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/* Send Read command. */
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hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
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(1 << HW_ATL_MDIO_OP_MODE_SHIFT) |
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((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
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HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
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/* Read result. */
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aq_mdio_busy_wait(aq_hw);
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return (u16)hw_atl_glb_mdio_iface5_get(aq_hw);
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}
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void aq_mdio_write_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr, u16 data)
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{
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u16 phy_addr = aq_hw->phy_id << 5 | mmd;
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/* Set Address register. */
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hw_atl_glb_mdio_iface4_set(aq_hw, (addr & HW_ATL_MDIO_ADDRESS_MSK) <<
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HW_ATL_MDIO_ADDRESS_SHIFT);
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/* Send Address command. */
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hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
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(3 << HW_ATL_MDIO_OP_MODE_SHIFT) |
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((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
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HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
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aq_mdio_busy_wait(aq_hw);
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hw_atl_glb_mdio_iface3_set(aq_hw, (data & HW_ATL_MDIO_WRITE_DATA_MSK) <<
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HW_ATL_MDIO_WRITE_DATA_SHIFT);
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/* Send Write command. */
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hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
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(2 << HW_ATL_MDIO_OP_MODE_SHIFT) |
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((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
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HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
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aq_mdio_busy_wait(aq_hw);
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}
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u16 aq_phy_read_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address)
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{
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int err = 0;
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u32 val;
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err = readx_poll_timeout_atomic(hw_atl_sem_mdio_get, aq_hw,
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val, val == 1U, 10U, 100000U);
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if (err < 0) {
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err = 0xffff;
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goto err_exit;
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}
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err = aq_mdio_read_word(aq_hw, mmd, address);
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hw_atl_reg_glb_cpu_sem_set(aq_hw, 1U, HW_ATL_FW_SM_MDIO);
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err_exit:
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return err;
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}
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void aq_phy_write_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address, u16 data)
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{
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int err = 0;
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u32 val;
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err = readx_poll_timeout_atomic(hw_atl_sem_mdio_get, aq_hw,
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val, val == 1U, 10U, 100000U);
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if (err < 0)
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return;
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aq_mdio_write_word(aq_hw, mmd, address, data);
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hw_atl_reg_glb_cpu_sem_set(aq_hw, 1U, HW_ATL_FW_SM_MDIO);
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}
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bool aq_phy_init_phy_id(struct aq_hw_s *aq_hw)
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{
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u16 val;
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for (aq_hw->phy_id = 0; aq_hw->phy_id < HW_ATL_PHY_ID_MAX;
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++aq_hw->phy_id) {
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/* PMA Standard Device Identifier 2: Address 1.3 */
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val = aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 3);
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if (val != 0xffff)
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return true;
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}
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return false;
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}
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bool aq_phy_init(struct aq_hw_s *aq_hw)
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{
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u32 dev_id;
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if (aq_hw->phy_id == HW_ATL_PHY_ID_MAX)
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if (!aq_phy_init_phy_id(aq_hw))
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return false;
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/* PMA Standard Device Identifier:
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* Address 1.2 = MSW,
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* Address 1.3 = LSW
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*/
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dev_id = aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 2);
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dev_id <<= 16;
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dev_id |= aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 3);
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if (dev_id == 0xffffffff) {
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aq_hw->phy_id = HW_ATL_PHY_ID_MAX;
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return false;
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}
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return true;
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}
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* aQuantia Corporation Network Driver
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* Copyright (C) 2018-2019 aQuantia Corporation. All rights reserved
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*/
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#ifndef AQ_PHY_H
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#define AQ_PHY_H
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#include <linux/mdio.h>
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#include "hw_atl/hw_atl_llh.h"
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#include "hw_atl/hw_atl_llh_internal.h"
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#include "aq_hw_utils.h"
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#include "aq_hw.h"
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#define HW_ATL_PHY_ID_MAX 32U
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bool aq_mdio_busy_wait(struct aq_hw_s *aq_hw);
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u16 aq_mdio_read_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr);
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void aq_mdio_write_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr, u16 data);
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u16 aq_phy_read_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address);
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void aq_phy_write_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address, u16 data);
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bool aq_phy_init_phy_id(struct aq_hw_s *aq_hw);
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bool aq_phy_init(struct aq_hw_s *aq_hw);
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#endif /* AQ_PHY_H */
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@ -1644,6 +1644,11 @@ u32 hw_atl_sem_ram_get(struct aq_hw_s *self)
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return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
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}
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u32 hw_atl_sem_mdio_get(struct aq_hw_s *self)
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{
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return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_MDIO);
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}
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u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp)
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{
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return aq_hw_read_reg(aq_hw,
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@ -1659,3 +1664,60 @@ u32 hw_atl_scrpad25_get(struct aq_hw_s *self)
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{
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return hw_atl_scrpad_get(self, 0x18);
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}
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void hw_atl_glb_mdio_iface1_set(struct aq_hw_s *aq_hw, u32 value)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1), value);
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}
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u32 hw_atl_glb_mdio_iface1_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1));
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}
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void hw_atl_glb_mdio_iface2_set(struct aq_hw_s *aq_hw, u32 value)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2), value);
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}
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u32 hw_atl_glb_mdio_iface2_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2));
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}
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void hw_atl_glb_mdio_iface3_set(struct aq_hw_s *aq_hw, u32 value)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3), value);
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}
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u32 hw_atl_glb_mdio_iface3_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3));
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}
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void hw_atl_glb_mdio_iface4_set(struct aq_hw_s *aq_hw, u32 value)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4), value);
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}
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u32 hw_atl_glb_mdio_iface4_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4));
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}
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void hw_atl_glb_mdio_iface5_set(struct aq_hw_s *aq_hw, u32 value)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5), value);
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}
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u32 hw_atl_glb_mdio_iface5_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5));
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}
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u32 hw_atl_mdio_busy_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg_bit(aq_hw, HW_ATL_MDIO_BUSY_ADR,
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HW_ATL_MDIO_BUSY_MSK,
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HW_ATL_MDIO_BUSY_SHIFT);
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}
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@ -767,9 +767,44 @@ void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
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void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 *ipv6_dest);
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/* set Global MDIO Interface 1 */
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void hw_atl_glb_mdio_iface1_set(struct aq_hw_s *hw, u32 value);
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/* get Global MDIO Interface 1 */
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u32 hw_atl_glb_mdio_iface1_get(struct aq_hw_s *hw);
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/* set Global MDIO Interface 2 */
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void hw_atl_glb_mdio_iface2_set(struct aq_hw_s *hw, u32 value);
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/* get Global MDIO Interface 2 */
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u32 hw_atl_glb_mdio_iface2_get(struct aq_hw_s *hw);
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/* set Global MDIO Interface 3 */
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void hw_atl_glb_mdio_iface3_set(struct aq_hw_s *hw, u32 value);
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/* get Global MDIO Interface 3 */
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u32 hw_atl_glb_mdio_iface3_get(struct aq_hw_s *hw);
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/* set Global MDIO Interface 4 */
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void hw_atl_glb_mdio_iface4_set(struct aq_hw_s *hw, u32 value);
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/* get Global MDIO Interface 4 */
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u32 hw_atl_glb_mdio_iface4_get(struct aq_hw_s *hw);
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/* set Global MDIO Interface 5 */
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void hw_atl_glb_mdio_iface5_set(struct aq_hw_s *hw, u32 value);
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/* get Global MDIO Interface 5 */
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u32 hw_atl_glb_mdio_iface5_get(struct aq_hw_s *hw);
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u32 hw_atl_mdio_busy_get(struct aq_hw_s *aq_hw);
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/* get global microprocessor ram semaphore */
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u32 hw_atl_sem_ram_get(struct aq_hw_s *self);
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/* get global microprocessor mdio semaphore */
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u32 hw_atl_sem_mdio_get(struct aq_hw_s *self);
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/* get global microprocessor scratch pad register */
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u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp);
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@ -2594,6 +2594,121 @@
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/* default value of bitfield uP Force Interrupt */
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#define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0
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/* Preprocessor definitions for Global MDIO Interfaces
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* Address: 0x00000280 + 0x4 * Number of interface
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*/
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#define HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN 0x00000280u
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#define HW_ATL_GLB_MDIO_IFACE_N_ADR(number) \
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(HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN + (((number) - 1) * 0x4))
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/* MIF MDIO Busy Bitfield Definitions
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* Preprocessor definitions for the bitfield "MDIO Busy".
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* PORT="mdio_pif_busy_o"
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*/
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/* Register address for bitfield MDIO Busy */
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#define HW_ATL_MDIO_BUSY_ADR 0x00000284
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/* Bitmask for bitfield MDIO Busy */
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#define HW_ATL_MDIO_BUSY_MSK 0x80000000
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/* Inverted bitmask for bitfield MDIO Busy */
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#define HW_ATL_MDIO_BUSY_MSKN 0x7FFFFFFF
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/* Lower bit position of bitfield MDIO Busy */
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#define HW_ATL_MDIO_BUSY_SHIFT 31
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/* Width of bitfield MDIO Busy */
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#define HW_ATL_MDIO_BUSY_WIDTH 1
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/* MIF MDIO Execute Operation Bitfield Definitions
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* Preprocessor definitions for the bitfield "MDIO Execute Operation".
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* PORT="pif_mdio_op_start_i"
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*/
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/* Register address for bitfield MDIO Execute Operation */
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#define HW_ATL_MDIO_EXECUTE_OPERATION_ADR 0x00000284
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/* Bitmask for bitfield MDIO Execute Operation */
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#define HW_ATL_MDIO_EXECUTE_OPERATION_MSK 0x00008000
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/* Inverted bitmask for bitfield MDIO Execute Operation */
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#define HW_ATL_MDIO_EXECUTE_OPERATION_MSKN 0xFFFF7FFF
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/* Lower bit position of bitfield MDIO Execute Operation */
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#define HW_ATL_MDIO_EXECUTE_OPERATION_SHIFT 15
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/* Width of bitfield MDIO Execute Operation */
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#define HW_ATL_MDIO_EXECUTE_OPERATION_WIDTH 1
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/* Default value of bitfield MDIO Execute Operation */
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#define HW_ATL_MDIO_EXECUTE_OPERATION_DEFAULT 0x0
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/* MIF Op Mode [1:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "Op Mode [1:0]".
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* PORT="pif_mdio_mode_i[1:0]"
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*/
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/* Register address for bitfield Op Mode [1:0] */
|
||||
#define HW_ATL_MDIO_OP_MODE_ADR 0x00000284
|
||||
/* Bitmask for bitfield Op Mode [1:0] */
|
||||
#define HW_ATL_MDIO_OP_MODE_MSK 0x00003000
|
||||
/* Inverted bitmask for bitfield Op Mode [1:0] */
|
||||
#define HW_ATL_MDIO_OP_MODE_MSKN 0xFFFFCFFF
|
||||
/* Lower bit position of bitfield Op Mode [1:0] */
|
||||
#define HW_ATL_MDIO_OP_MODE_SHIFT 12
|
||||
/* Width of bitfield Op Mode [1:0] */
|
||||
#define HW_ATL_MDIO_OP_MODE_WIDTH 2
|
||||
/* Default value of bitfield Op Mode [1:0] */
|
||||
#define HW_ATL_MDIO_OP_MODE_DEFAULT 0x0
|
||||
|
||||
/* MIF PHY address Bitfield Definitions
|
||||
* Preprocessor definitions for the bitfield "PHY address".
|
||||
* PORT="pif_mdio_phy_addr_i[9:0]"
|
||||
*/
|
||||
|
||||
/* Register address for bitfield PHY address */
|
||||
#define HW_ATL_MDIO_PHY_ADDRESS_ADR 0x00000284
|
||||
/* Bitmask for bitfield PHY address */
|
||||
#define HW_ATL_MDIO_PHY_ADDRESS_MSK 0x000003FF
|
||||
/* Inverted bitmask for bitfield PHY address */
|
||||
#define HW_ATL_MDIO_PHY_ADDRESS_MSKN 0xFFFFFC00
|
||||
/* Lower bit position of bitfield PHY address */
|
||||
#define HW_ATL_MDIO_PHY_ADDRESS_SHIFT 0
|
||||
/* Width of bitfield PHY address */
|
||||
#define HW_ATL_MDIO_PHY_ADDRESS_WIDTH 10
|
||||
/* Default value of bitfield PHY address */
|
||||
#define HW_ATL_MDIO_PHY_ADDRESS_DEFAULT 0x0
|
||||
|
||||
/* MIF MDIO WriteData [F:0] Bitfield Definitions
|
||||
* Preprocessor definitions for the bitfield "MDIO WriteData [F:0]".
|
||||
* PORT="pif_mdio_wdata_i[15:0]"
|
||||
*/
|
||||
|
||||
/* Register address for bitfield MDIO WriteData [F:0] */
|
||||
#define HW_ATL_MDIO_WRITE_DATA_ADR 0x00000288
|
||||
/* Bitmask for bitfield MDIO WriteData [F:0] */
|
||||
#define HW_ATL_MDIO_WRITE_DATA_MSK 0x0000FFFF
|
||||
/* Inverted bitmask for bitfield MDIO WriteData [F:0] */
|
||||
#define HW_ATL_MDIO_WRITE_DATA_MSKN 0xFFFF0000
|
||||
/* Lower bit position of bitfield MDIO WriteData [F:0] */
|
||||
#define HW_ATL_MDIO_WRITE_DATA_SHIFT 0
|
||||
/* Width of bitfield MDIO WriteData [F:0] */
|
||||
#define HW_ATL_MDIO_WRITE_DATA_WIDTH 16
|
||||
/* Default value of bitfield MDIO WriteData [F:0] */
|
||||
#define HW_ATL_MDIO_WRITE_DATA_DEFAULT 0x0
|
||||
|
||||
/* MIF MDIO Address [F:0] Bitfield Definitions
|
||||
* Preprocessor definitions for the bitfield "MDIO Address [F:0]".
|
||||
* PORT="pif_mdio_addr_i[15:0]"
|
||||
*/
|
||||
|
||||
/* Register address for bitfield MDIO Address [F:0] */
|
||||
#define HW_ATL_MDIO_ADDRESS_ADR 0x0000028C
|
||||
/* Bitmask for bitfield MDIO Address [F:0] */
|
||||
#define HW_ATL_MDIO_ADDRESS_MSK 0x0000FFFF
|
||||
/* Inverted bitmask for bitfield MDIO Address [F:0] */
|
||||
#define HW_ATL_MDIO_ADDRESS_MSKN 0xFFFF0000
|
||||
/* Lower bit position of bitfield MDIO Address [F:0] */
|
||||
#define HW_ATL_MDIO_ADDRESS_SHIFT 0
|
||||
/* Width of bitfield MDIO Address [F:0] */
|
||||
#define HW_ATL_MDIO_ADDRESS_WIDTH 16
|
||||
/* Default value of bitfield MDIO Address [F:0] */
|
||||
#define HW_ATL_MDIO_ADDRESS_DEFAULT 0x0
|
||||
|
||||
#define HW_ATL_FW_SM_MDIO 0x0U
|
||||
#define HW_ATL_FW_SM_RAM 0x2U
|
||||
|
||||
#endif /* HW_ATL_LLH_INTERNAL_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue