Revert "clk: bcm2835: remove pllb"
This reverts commit 2256d89333
. Since we
will be expanding the firmware clock driver, we'll need to remove the
quirks to deal with the PLLB. However, we still want to expose the clock
tree properly, so having that clock in the MMIO driver will allow that.
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/5d26a4c58248f5be7760a7f2f720a1310baea5dd.1592210452.git-series.maxime@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
7dad8a6131
commit
dbe01b4412
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@ -1684,10 +1684,32 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.fixed_divider = 1,
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.flags = CLK_SET_RATE_PARENT),
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/*
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* PLLB is used for the ARM's clock. Controlled by firmware, see
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* clk-raspberrypi.c.
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*/
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/* PLLB is used for the ARM's clock. */
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[BCM2835_PLLB] = REGISTER_PLL(
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SOC_ALL,
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.name = "pllb",
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.cm_ctrl_reg = CM_PLLB,
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.a2w_ctrl_reg = A2W_PLLB_CTRL,
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.frac_reg = A2W_PLLB_FRAC,
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.ana_reg_base = A2W_PLLB_ANA0,
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.reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
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.lock_mask = CM_LOCK_FLOCKB,
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.ana = &bcm2835_ana_default,
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.min_rate = 600000000u,
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.max_rate = 3000000000u,
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.max_fb_rate = BCM2835_MAX_FB_RATE),
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[BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
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SOC_ALL,
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.name = "pllb_arm",
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.source_pll = "pllb",
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.cm_reg = CM_PLLB,
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.a2w_reg = A2W_PLLB_ARM,
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.load_mask = CM_PLLB_LOADARM,
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.hold_mask = CM_PLLB_HOLDARM,
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.fixed_divider = 1,
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.flags = CLK_SET_RATE_PARENT),
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/*
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* PLLC is the core PLL, used to drive the core VPU clock.
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