clk: tegra: periph: Add new periph clks and muxes for Tegra210
Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>hifive-unleashed-5.1
Rhyland Klein
Thierry Reding
parent
385f9adf62
commit
dc37fec483
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@ -13,6 +13,7 @@ enum clk_id {
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tegra_clk_amx1,
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tegra_clk_apbdma,
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tegra_clk_apbif,
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tegra_clk_ape,
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tegra_clk_audio0,
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tegra_clk_audio0_2x,
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tegra_clk_audio0_mux,
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@ -38,6 +39,7 @@ enum clk_id {
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tegra_clk_cile,
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tegra_clk_clk_32k,
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tegra_clk_clk72Mhz,
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tegra_clk_clk72Mhz_8,
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tegra_clk_clk_m,
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tegra_clk_clk_m_div2,
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tegra_clk_clk_m_div4,
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@ -51,17 +53,21 @@ enum clk_id {
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tegra_clk_cml1,
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tegra_clk_csi,
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tegra_clk_csite,
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tegra_clk_csite_8,
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tegra_clk_csus,
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tegra_clk_cve,
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tegra_clk_dam0,
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tegra_clk_dam1,
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tegra_clk_dam2,
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tegra_clk_d_audio,
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tegra_clk_dbgapb,
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tegra_clk_dds,
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tegra_clk_dfll_ref,
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tegra_clk_dfll_soc,
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tegra_clk_disp1,
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tegra_clk_disp1_8,
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tegra_clk_disp2,
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tegra_clk_disp2_8,
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tegra_clk_dp2,
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tegra_clk_dpaux,
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tegra_clk_dsialp,
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@ -71,6 +77,7 @@ enum clk_id {
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tegra_clk_dtv,
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tegra_clk_emc,
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tegra_clk_entropy,
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tegra_clk_entropy_8,
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tegra_clk_epp,
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tegra_clk_epp_8,
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tegra_clk_extern1,
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@ -85,12 +92,16 @@ enum clk_id {
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tegra_clk_gr3d_8,
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tegra_clk_hclk,
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tegra_clk_hda,
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tegra_clk_hda_8,
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tegra_clk_hda2codec_2x,
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tegra_clk_hda2codec_2x_8,
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tegra_clk_hda2hdmi,
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tegra_clk_hdmi,
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tegra_clk_hdmi_audio,
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tegra_clk_host1x,
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tegra_clk_host1x_8,
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tegra_clk_host1x_9,
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tegra_clk_hsic_trk,
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tegra_clk_i2c1,
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tegra_clk_i2c2,
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tegra_clk_i2c3,
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@ -110,11 +121,14 @@ enum clk_id {
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tegra_clk_i2s4_sync,
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tegra_clk_isp,
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tegra_clk_isp_8,
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tegra_clk_isp_9,
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tegra_clk_ispb,
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tegra_clk_kbc,
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tegra_clk_kfuse,
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tegra_clk_la,
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tegra_clk_maud,
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tegra_clk_mipi,
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tegra_clk_mipibif,
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tegra_clk_mipi_cal,
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tegra_clk_mpe,
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tegra_clk_mselect,
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@ -124,11 +138,16 @@ enum clk_id {
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tegra_clk_ndspeed,
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tegra_clk_ndspeed_8,
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tegra_clk_nor,
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tegra_clk_nvdec,
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tegra_clk_nvenc,
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tegra_clk_nvjpg,
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tegra_clk_owr,
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tegra_clk_owr_8,
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tegra_clk_pcie,
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tegra_clk_pclk,
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tegra_clk_pll_a,
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tegra_clk_pll_a_out0,
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tegra_clk_pll_a1,
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tegra_clk_pll_c,
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tegra_clk_pll_c2,
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tegra_clk_pll_c3,
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@ -140,15 +159,22 @@ enum clk_id {
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tegra_clk_pll_d_out0,
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tegra_clk_pll_dp,
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tegra_clk_pll_e_out0,
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tegra_clk_pll_g_ref,
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tegra_clk_pll_m,
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tegra_clk_pll_m_out1,
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tegra_clk_pll_mb,
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tegra_clk_pll_p,
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tegra_clk_pll_p_out1,
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tegra_clk_pll_p_out2,
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tegra_clk_pll_p_out2_int,
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tegra_clk_pll_p_out3,
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tegra_clk_pll_p_out4,
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tegra_clk_pll_p_out4_cpu,
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tegra_clk_pll_p_out5,
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tegra_clk_pll_p_out_hsio,
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tegra_clk_pll_p_out_xusb,
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tegra_clk_pll_p_out_cpu,
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tegra_clk_pll_p_out_adsp,
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tegra_clk_pll_ref,
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tegra_clk_pll_re_out,
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tegra_clk_pll_re_vco,
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@ -160,53 +186,80 @@ enum clk_id {
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tegra_clk_pll_x,
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tegra_clk_pll_x_out0,
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tegra_clk_pwm,
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tegra_clk_qspi,
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tegra_clk_rtc,
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tegra_clk_sata,
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tegra_clk_sata_8,
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tegra_clk_sata_cold,
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tegra_clk_sata_oob,
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tegra_clk_sata_oob_8,
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tegra_clk_sbc1,
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tegra_clk_sbc1_8,
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tegra_clk_sbc1_9,
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tegra_clk_sbc2,
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tegra_clk_sbc2_8,
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tegra_clk_sbc2_9,
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tegra_clk_sbc3,
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tegra_clk_sbc3_8,
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tegra_clk_sbc3_9,
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tegra_clk_sbc4,
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tegra_clk_sbc4_8,
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tegra_clk_sbc4_9,
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tegra_clk_sbc5,
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tegra_clk_sbc5_8,
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tegra_clk_sbc6,
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tegra_clk_sbc6_8,
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tegra_clk_sclk,
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tegra_clk_sdmmc_legacy,
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tegra_clk_sdmmc1,
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tegra_clk_sdmmc1_8,
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tegra_clk_sdmmc1_9,
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tegra_clk_sdmmc2,
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tegra_clk_sdmmc2_8,
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tegra_clk_sdmmc2_9,
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tegra_clk_sdmmc3,
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tegra_clk_sdmmc3_8,
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tegra_clk_sdmmc3_9,
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tegra_clk_sdmmc4,
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tegra_clk_sdmmc4_8,
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tegra_clk_sdmmc4_9,
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tegra_clk_se,
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tegra_clk_soc_therm,
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tegra_clk_soc_therm_8,
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tegra_clk_sor0,
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tegra_clk_sor0_lvds,
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tegra_clk_sor1,
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tegra_clk_sor1_brick,
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tegra_clk_sor1_src,
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tegra_clk_spdif,
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tegra_clk_spdif_2x,
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tegra_clk_spdif_in,
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tegra_clk_spdif_in_8,
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tegra_clk_spdif_in_sync,
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tegra_clk_spdif_mux,
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tegra_clk_spdif_out,
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tegra_clk_timer,
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tegra_clk_trace,
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tegra_clk_tsec,
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tegra_clk_tsec_8,
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tegra_clk_tsecb,
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tegra_clk_tsensor,
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tegra_clk_tvdac,
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tegra_clk_tvo,
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tegra_clk_uarta,
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tegra_clk_uarta_8,
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tegra_clk_uartb,
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tegra_clk_uartb_8,
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tegra_clk_uartc,
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tegra_clk_uartc_8,
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tegra_clk_uartd,
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tegra_clk_uartd_8,
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tegra_clk_uarte,
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tegra_clk_uarte_8,
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tegra_clk_uartape,
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tegra_clk_usb2,
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tegra_clk_usb2_hsic_trk,
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tegra_clk_usb2_trk,
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tegra_clk_usb3,
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tegra_clk_usbd,
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tegra_clk_vcp,
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@ -216,22 +269,35 @@ enum clk_id {
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tegra_clk_vi,
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tegra_clk_vi_8,
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tegra_clk_vi_9,
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tegra_clk_vi_10,
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tegra_clk_vi_i2c,
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tegra_clk_vic03,
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tegra_clk_vic03_8,
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tegra_clk_vim2_clk,
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tegra_clk_vimclk_sync,
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tegra_clk_vi_sensor,
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tegra_clk_vi_sensor2,
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tegra_clk_vi_sensor_8,
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tegra_clk_vi_sensor_9,
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tegra_clk_vi_sensor2,
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tegra_clk_vi_sensor2_8,
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tegra_clk_xusb_dev,
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tegra_clk_xusb_dev_src,
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tegra_clk_xusb_dev_src_8,
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tegra_clk_xusb_falcon_src,
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tegra_clk_xusb_falcon_src_8,
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tegra_clk_xusb_fs_src,
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tegra_clk_xusb_gate,
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tegra_clk_xusb_host,
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tegra_clk_xusb_host_src,
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tegra_clk_xusb_host_src_8,
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tegra_clk_xusb_hs_src,
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tegra_clk_xusb_hs_src_4,
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tegra_clk_xusb_ss,
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tegra_clk_xusb_ss_src,
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tegra_clk_xusb_ss_src_8,
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tegra_clk_xusb_ss_div2,
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tegra_clk_xusb_ssp_src,
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tegra_clk_sclk_mux,
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tegra_clk_max,
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};
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@ -124,6 +124,20 @@
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#define CLK_SOURCE_HDMI_AUDIO 0x668
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#define CLK_SOURCE_VIC03 0x678
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#define CLK_SOURCE_CLK72MHZ 0x66c
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#define CLK_SOURCE_DBGAPB 0x718
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#define CLK_SOURCE_NVENC 0x6a0
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#define CLK_SOURCE_NVDEC 0x698
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#define CLK_SOURCE_NVJPG 0x69c
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#define CLK_SOURCE_APE 0x6c0
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#define CLK_SOURCE_SOR1 0x410
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#define CLK_SOURCE_SDMMC_LEGACY 0x694
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#define CLK_SOURCE_QSPI 0x6c4
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#define CLK_SOURCE_VI_I2C 0x6c8
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#define CLK_SOURCE_MIPIBIF 0x660
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#define CLK_SOURCE_UARTAPE 0x710
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#define CLK_SOURCE_TSECB 0x6d8
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#define CLK_SOURCE_MAUD 0x6d4
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#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
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#define MASK(x) (BIT(x) - 1)
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@ -182,6 +196,13 @@
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TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
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_parents##_idx, 0, NULL)
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#define UART8(_name, _parents, _offset,\
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_clk_num, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
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TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
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_parents##_idx, 0, NULL)
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#define I2C(_name, _parents, _offset,\
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_clk_num, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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@ -221,8 +242,21 @@
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.flags = _flags \
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}
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#define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \
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{ \
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.name = _name, \
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.clk_id = _clk_id, \
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.p.parent_name = _parent_name, \
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.periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1, \
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TEGRA_DIVIDER_ROUND_UP, 0, 0, \
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NULL, NULL), \
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.offset = _offset, \
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.flags = _flags, \
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}
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#define PLLP_BASE 0xa0
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#define PLLP_MISC 0xac
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#define PLLP_MISC1 0x680
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#define PLLP_OUTA 0xa4
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#define PLLP_OUTB 0xa8
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#define PLLP_OUTC 0x67c
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@ -234,6 +268,7 @@ static DEFINE_SPINLOCK(PLLP_OUTA_lock);
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static DEFINE_SPINLOCK(PLLP_OUTB_lock);
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static DEFINE_SPINLOCK(PLLP_OUTC_lock);
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static DEFINE_SPINLOCK(sor0_lock);
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static DEFINE_SPINLOCK(sor1_lock);
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#define MUX_I2S_SPDIF(_id) \
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static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
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@ -285,6 +320,68 @@ static u32 mux_pllp_clkm_idx[] = {
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[0] = 0, [1] = 3,
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};
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static const char *mux_pllp_clkm_2[] = {
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"pll_p", "clk_m"
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};
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static u32 mux_pllp_clkm_2_idx[] = {
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[0] = 2, [1] = 6,
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};
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static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = {
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"pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
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};
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static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = {
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[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7,
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};
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static const char *
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mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = {
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"pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
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"pll_a_out0", "pll_c4_out0"
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};
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static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = {
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[0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
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};
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static const char *mux_pllc_pllp_plla[] = {
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"pll_c", "pll_p", "pll_a_out0"
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};
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static u32 mux_pllc_pllp_plla_idx[] = {
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[0] = 1, [1] = 2, [2] = 3,
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};
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static const char *mux_clkm_pllc_pllp_plla[] = {
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"clk_m", "pll_c", "pll_p", "pll_a_out0"
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};
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#define mux_clkm_pllc_pllp_plla_idx NULL
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static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = {
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"pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m"
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};
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static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = {
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[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6,
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};
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static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = {
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"pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0",
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};
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static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = {
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[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
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};
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static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = {
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"pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0",
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};
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#define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \
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mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx
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static const char *
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mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = {
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"pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p",
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"pll_c4_out2", "clk_m"
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};
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#define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL
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static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
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"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
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};
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@ -302,12 +399,93 @@ static const char *mux_pllm_pllc_pllp_plla[] = {
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#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
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static const char *mux_pllp_pllc_clkm[] = {
|
||||
"pll_p", "pll_c", "pll_m"
|
||||
"pll_p", "pll_c", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_pllc_clkm_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 3,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc_clkm_1[] = {
|
||||
"pll_p", "pll_c", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_pllc_clkm_1_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 5,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc_plla_clkm[] = {
|
||||
"pll_p", "pll_c", "pll_a_out0", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_pllc_plla_clkm_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 4, [3] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = {
|
||||
"pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2"
|
||||
};
|
||||
static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7,
|
||||
};
|
||||
|
||||
static const char *
|
||||
mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
|
||||
"pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1",
|
||||
"clk_m", "pll_c4_out0"
|
||||
};
|
||||
static u32
|
||||
mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
|
||||
"pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0"
|
||||
};
|
||||
static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
|
||||
[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
|
||||
"pll_p",
|
||||
"pll_c4_out2", "pll_c4_out0", /* LJ input */
|
||||
"pll_c4_out2", "pll_c4_out1",
|
||||
"pll_c4_out1", /* LJ input */
|
||||
"clk_m", "pll_c4_out0"
|
||||
};
|
||||
#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
|
||||
|
||||
static const char *mux_pllp_pllc2_c_c3_clkm[] = {
|
||||
"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_clkm_clk32_plle[] = {
|
||||
"pll_p", "clk_m", "clk_32k", "pll_e"
|
||||
};
|
||||
static u32 mux_pllp_clkm_clk32_plle_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 4, [3] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = {
|
||||
"pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
|
||||
};
|
||||
#define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL
|
||||
|
||||
static const char *mux_pllp_out3_clkm_pllp_pllc4[] = {
|
||||
"pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1",
|
||||
"pll_c4_out2"
|
||||
};
|
||||
static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = {
|
||||
[0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_clkm_pllp_pllre[] = {
|
||||
"clk_m", "pll_p_out_xusb", "pll_re_out"
|
||||
};
|
||||
static u32 mux_clkm_pllp_pllre_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 5,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc_clkm_clk32[] = {
|
||||
"pll_p", "pll_c", "clk_m", "clk_32k"
|
||||
};
|
||||
|
|
@ -332,6 +510,11 @@ static u32 mux_clkm_48M_pllp_480M_idx[] = {
|
|||
[0] = 0, [1] = 2, [2] = 4, [3] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_clkm_pllre_clk32_480M[] = {
|
||||
"clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
|
||||
};
|
||||
#define mux_clkm_pllre_clk32_480M_idx NULL
|
||||
|
||||
static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
|
||||
"clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
|
||||
};
|
||||
|
|
@ -339,10 +522,27 @@ static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
|
|||
[0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_ss_60M[] = {
|
||||
static const char *mux_pllp_out3_pllp_pllc_clkm[] = {
|
||||
"pll_p_out3", "pll_p", "pll_c", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 2, [3] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_ss_div2_60M[] = {
|
||||
"xusb_ss_div2", "pll_u_60M"
|
||||
};
|
||||
#define mux_ss_60M_idx NULL
|
||||
#define mux_ss_div2_60M_idx NULL
|
||||
|
||||
static const char *mux_ss_div2_60M_ss[] = {
|
||||
"xusb_ss_div2", "pll_u_60M", "xusb_ss_src"
|
||||
};
|
||||
#define mux_ss_div2_60M_ss_idx NULL
|
||||
|
||||
static const char *mux_ss_clkm[] = {
|
||||
"xusb_ss_src", "clk_m"
|
||||
};
|
||||
#define mux_ss_clkm_idx NULL
|
||||
|
||||
static const char *mux_d_audio_clk[] = {
|
||||
"pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
|
||||
|
|
@ -386,6 +586,32 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
|
|||
[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
|
||||
};
|
||||
|
||||
/* SOR1 mux'es */
|
||||
static const char *mux_pllp_plld_plld2_clkm[] = {
|
||||
"pll_p", "pll_d_out0", "pll_d2_out0", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_plld_plld2_clkm_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 5, [3] = 6
|
||||
};
|
||||
|
||||
static const char *mux_plldp_sor1_src[] = {
|
||||
"pll_dp", "clk_sor1_src"
|
||||
};
|
||||
#define mux_plldp_sor1_src_idx NULL
|
||||
|
||||
static const char *mux_clkm_sor1_brick_sor1_src[] = {
|
||||
"clk_m", "sor1_brick", "sor1_src", "sor1_brick"
|
||||
};
|
||||
#define mux_clkm_sor1_brick_sor1_src_idx NULL
|
||||
|
||||
static const char *mux_pllp_pllre_clkm[] = {
|
||||
"pll_p", "pll_re_out1", "clk_m"
|
||||
};
|
||||
|
||||
static u32 mux_pllp_pllre_clkm_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 3,
|
||||
};
|
||||
|
||||
static const char *mux_clkm_plldp_sor0lvds[] = {
|
||||
"clk_m", "pll_dp", "sor0_lvds",
|
||||
};
|
||||
|
|
@ -401,6 +627,7 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
|
||||
I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
|
||||
I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
|
||||
I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
|
||||
INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
|
||||
INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
|
||||
INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
|
||||
|
|
@ -411,14 +638,19 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
|
||||
INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
|
||||
INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
|
||||
INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10),
|
||||
INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
|
||||
INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
|
||||
INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
|
||||
INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8),
|
||||
INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
|
||||
INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),
|
||||
INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
|
||||
INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
|
||||
INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
|
||||
INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
|
||||
INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
|
||||
INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8),
|
||||
INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
|
||||
MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
|
||||
MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
|
||||
|
|
@ -427,22 +659,31 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
|
||||
MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
|
||||
MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
|
||||
MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8),
|
||||
MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
|
||||
MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
|
||||
MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
|
||||
MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
|
||||
MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8),
|
||||
MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
|
||||
MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8),
|
||||
MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
|
||||
MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
|
||||
MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
|
||||
MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
|
||||
MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
|
||||
MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
|
||||
MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
|
||||
MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
|
||||
MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
|
||||
MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
|
||||
MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
|
||||
MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
|
||||
MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8),
|
||||
MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
|
||||
MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
|
||||
MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
|
||||
MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9),
|
||||
MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
|
||||
MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
|
||||
MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
|
||||
|
|
@ -465,10 +706,13 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
|
||||
MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
|
||||
MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
|
||||
MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8),
|
||||
MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
|
||||
MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8),
|
||||
MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
|
||||
MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
|
||||
MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
|
||||
MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8),
|
||||
MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
|
||||
MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
|
||||
MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
|
||||
|
|
@ -479,6 +723,10 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
|
||||
MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
|
||||
MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
|
||||
MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9),
|
||||
MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9),
|
||||
MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9),
|
||||
MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9),
|
||||
MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
|
||||
MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
|
||||
MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
|
||||
|
|
@ -486,27 +734,59 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
|
||||
MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
|
||||
MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
|
||||
MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
|
||||
MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
|
||||
MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
|
||||
MUX8("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_9),
|
||||
MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
|
||||
MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
|
||||
MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
|
||||
MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
|
||||
MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
|
||||
MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
|
||||
MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
|
||||
MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
|
||||
NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
|
||||
NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
|
||||
NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
|
||||
NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
|
||||
NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
|
||||
UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
|
||||
UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
|
||||
UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
|
||||
UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
|
||||
UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
|
||||
UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8),
|
||||
UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8),
|
||||
UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8),
|
||||
UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8),
|
||||
XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
|
||||
XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8),
|
||||
XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
|
||||
XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8),
|
||||
XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
|
||||
XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
|
||||
NODIV("xusb_hs_src", mux_ss_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
|
||||
XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8),
|
||||
NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
|
||||
NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL),
|
||||
NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL),
|
||||
XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
|
||||
XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
|
||||
MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
|
||||
MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
|
||||
MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
|
||||
MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
|
||||
MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
|
||||
MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
|
||||
NODIV("sor1_brick", mux_plldp_sor1_src, CLK_SOURCE_SOR1, 14, MASK(1), 183, 0, tegra_clk_sor1_brick, &sor1_lock),
|
||||
NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),
|
||||
MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
|
||||
MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
|
||||
MUX("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, TEGRA_PERIPH_ON_APB, tegra_clk_vi_i2c),
|
||||
MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
|
||||
MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
|
||||
MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
|
||||
MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
|
||||
};
|
||||
|
||||
static struct tegra_periph_init_data gate_clks[] = {
|
||||
|
|
@ -543,6 +823,16 @@ static struct tegra_periph_init_data gate_clks[] = {
|
|||
GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
|
||||
GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
|
||||
GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
|
||||
GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
|
||||
GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
|
||||
GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
|
||||
GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
|
||||
GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
|
||||
GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
|
||||
};
|
||||
|
||||
static struct tegra_periph_init_data div_clks[] = {
|
||||
DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0),
|
||||
};
|
||||
|
||||
struct pll_out_data {
|
||||
|
|
@ -633,6 +923,33 @@ static void __init gate_clk_init(void __iomem *clk_base,
|
|||
}
|
||||
}
|
||||
|
||||
static void __init div_clk_init(void __iomem *clk_base,
|
||||
struct tegra_clk *tegra_clks)
|
||||
{
|
||||
int i;
|
||||
struct clk *clk;
|
||||
struct clk **dt_clk;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(div_clks); i++) {
|
||||
struct tegra_periph_init_data *data;
|
||||
|
||||
data = div_clks + i;
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
|
||||
if (!dt_clk)
|
||||
continue;
|
||||
|
||||
clk = tegra_clk_register_divider(data->name,
|
||||
data->p.parent_name, clk_base + data->offset,
|
||||
data->flags, data->periph.divider.flags,
|
||||
data->periph.divider.shift,
|
||||
data->periph.divider.width,
|
||||
data->periph.divider.frac_width,
|
||||
data->periph.divider.lock);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *pll_params)
|
||||
|
|
@ -669,6 +986,51 @@ static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
|
|||
data->lock);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
|
||||
tegra_clks);
|
||||
if (dt_clk) {
|
||||
/*
|
||||
* Tegra210 has control on enabling/disabling PLLP branches to
|
||||
* CPU, register a gate clock "pll_p_out_cpu" for this gating
|
||||
* function and parent "pll_p_out4" to it, so when we are
|
||||
* re-parenting CPU off from "pll_p_out4" the PLLP branching to
|
||||
* CPU can be disabled automatically.
|
||||
*/
|
||||
clk = tegra_clk_register_divider("pll_p_out4_div",
|
||||
"pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
|
||||
8, 1, &PLLP_OUTB_lock);
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = tegra_clk_register_pll_out("pll_p_out4",
|
||||
"pll_p_out4_div", clk_base + PLLP_OUTB,
|
||||
17, 16, CLK_IGNORE_UNUSED |
|
||||
CLK_SET_RATE_PARENT, 0,
|
||||
&PLLP_OUTB_lock);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
|
||||
if (dt_clk) {
|
||||
/* PLLP_OUT_HSIO */
|
||||
clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
|
||||
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
clk_base + PLLP_MISC1, 29, 0, NULL);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
|
||||
if (dt_clk) {
|
||||
/* PLLP_OUT_XUSB */
|
||||
clk = clk_register_gate(NULL, "pll_p_out_xusb",
|
||||
"pll_p_out_hsio", CLK_SET_RATE_PARENT |
|
||||
CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
|
||||
NULL);
|
||||
clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
void __init tegra_periph_clk_init(void __iomem *clk_base,
|
||||
|
|
@ -678,4 +1040,5 @@ void __init tegra_periph_clk_init(void __iomem *clk_base,
|
|||
init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
|
||||
periph_clk_init(clk_base, tegra_clks);
|
||||
gate_clk_init(clk_base, tegra_clks);
|
||||
div_clk_init(clk_base, tegra_clks);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue