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drm/amd/powerplay: implement is_support_sw_smu function for new smu 

add this helper to check new sw-smu support.

Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.2
Kevin Wang 2019-01-10 12:33:23 +08:00 committed by Alex Deucher
parent dbe6a97024
commit dc8e3a0c8e
4 changed files with 21 additions and 9 deletions
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4
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
View File

@ -712,7 +712,7 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
if (adev->smu.ppt_funcs)
if (is_support_sw_smu(adev))
return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
@ -786,7 +786,7 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
if (adev->smu.ppt_funcs)
if (is_support_sw_smu(adev))
return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);

2
drivers/gpu/drm/amd/amdgpu/soc15.c
View File

@ -605,7 +605,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
if (!amdgpu_sriov_vf(adev)) {
if (amdgpu_dpm == 1 && adev->asic_type >= CHIP_VEGA20)
if (is_support_sw_smu(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
else
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);

23
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -65,6 +65,17 @@ int smu_update_table(struct smu_context *smu, uint32_t table_id,
return ret;
}
bool is_support_sw_smu(struct amdgpu_device *adev)
{
if (amdgpu_dpm != 1)
return false;
if (adev->asic_type >= CHIP_VEGA20)
return true;
return false;
}
int smu_feature_init_dpm(struct smu_context *smu)
{
struct smu_feature *feature = &smu->smu_feature;
@ -222,7 +233,7 @@ static int smu_sw_init(void *handle)
struct smu_context *smu = &adev->smu;
int ret;
if (adev->asic_type < CHIP_VEGA20)
if (!is_support_sw_smu(adev))
return -EINVAL;
smu->pool_size = adev->pm.smu_prv_buffer_size;
@ -252,7 +263,7 @@ static int smu_sw_fini(void *handle)
struct smu_context *smu = &adev->smu;
int ret;
if (adev->asic_type < CHIP_VEGA20)
if (!is_support_sw_smu(adev))
return -EINVAL;
ret = smu_smc_table_sw_fini(smu);
@ -517,7 +528,7 @@ static int smu_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
if (adev->asic_type < CHIP_VEGA20)
if (!is_support_sw_smu(adev))
return -EINVAL;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
@ -576,7 +587,7 @@ static int smu_hw_fini(void *handle)
struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
if (adev->asic_type < CHIP_VEGA20)
if (!is_support_sw_smu(adev))
return -EINVAL;
if (!table_context->driver_pptable)
@ -603,7 +614,7 @@ static int smu_suspend(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->asic_type < CHIP_VEGA20)
if (!is_support_sw_smu(adev))
return -EINVAL;
return 0;
@ -615,7 +626,7 @@ static int smu_resume(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
if (adev->asic_type < CHIP_VEGA20)
if (!is_support_sw_smu(adev))
return -EINVAL;
pr_info("SMU is resuming...\n");

1
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -366,5 +366,6 @@ extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bo
int smu_update_table(struct smu_context *smu, uint32_t table_id,
void *table_data, bool drv2smu);
bool is_support_sw_smu(struct amdgpu_device *adev);
#endif