drm/i915: use gtfifodbg
Add register definitions for GTFIFODBG, and clear it during init time to make sure state is correct. This register tells us if either a read, or a write occurred while the fifo was full. It seems like bit 2 is an OR of bit 0 and bit 1, so we check that as well, but the documents are not quite clear. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by (v1): Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3703,6 +3703,12 @@
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#define ECOBUS 0xa180
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#define FORCEWAKE_MT_ENABLE (1<<5)
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#define GTFIFODBG 0x120000
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#define GT_FIFO_CPU_ERROR_MASK 7
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#define GT_FIFO_OVFERR (1<<2)
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#define GT_FIFO_IAWRERR (1<<1)
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#define GT_FIFO_IARDERR (1<<0)
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#define GT_FIFO_FREE_ENTRIES 0x120008
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#define GT_FIFO_NUM_RESERVED_ENTRIES 20
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@ -8241,6 +8241,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
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u32 pcu_mbox, rc6_mask = 0;
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u32 gtfifodbg;
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int cur_freq, min_freq, max_freq;
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int i;
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@ -8252,6 +8253,13 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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*/
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I915_WRITE(GEN6_RC_STATE, 0);
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mutex_lock(&dev_priv->dev->struct_mutex);
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/* Clear the DBG now so we don't confuse earlier errors */
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if ((gtfifodbg = I915_READ(GTFIFODBG))) {
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DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
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I915_WRITE(GTFIFODBG, gtfifodbg);
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}
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gen6_gt_force_wake_get(dev_priv);
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/* disable the counters and set deterministic thresholds */
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