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Documentation: dt: net: fix spelling mistakes 

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Rob Herring <robh@kernel.org>
hifive-unleashed-5.1
Eric Engestrom 2016-04-25 01:24:15 +01:00 committed by Rob Herring
parent c7292b471b
commit dd346f2728
3 changed files with 4 additions and 4 deletions
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2
Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt
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@ -8,7 +8,7 @@ Required properties:
specifies a reference to the associating hardware driver node.
see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
- port-id: is the index of port provided by DSAF (the accelerator). DSAF can
connect to 8 PHYs. Port 0 to 1 are both used for adminstration purpose. They
connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
are called debug ports.
The remaining 6 PHYs are taken according to the mode of DSAF.

4
Documentation/devicetree/bindings/net/stmmac.txt
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@ -51,8 +51,8 @@ Optional properties:
AXI register inside the DMA module:
- snps,lpi_en: enable Low Power Interface
- snps,xit_frm: unlock on WoL
- snps,wr_osr_lmt: max write oustanding req. limit
- snps,rd_osr_lmt: max read oustanding req. limit
- snps,wr_osr_lmt: max write outstanding req. limit
- snps,rd_osr_lmt: max read outstanding req. limit
- snps,kbbe: do not cross 1KiB boundary.
- snps,axi_all: align address
- snps,blen: this is a vector of supported burst length.

2
Documentation/devicetree/bindings/net/ti,dp83867.txt
View File

@ -2,7 +2,7 @@
Required properties:
- reg - The ID number for the phy, usually a small integer
- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
- ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values