[PATCH] sl82c105: straighten up IDE control/status register caching
Straighten up the IDE control/status register caching -- you *really* can't cache the shared register per-channel and hope that it won't get out ouf sync. Set the PIO fallback mode to PIO0 for the slave drive as well as master -- there was no point in having them different (most probably a resutl of typo). Do a bit of reformat and cleanup while at it... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Acked-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -299,14 +299,14 @@ static void sl82c105_selectproc(ide_drive_t *drive)
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//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
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mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
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old = val = *((u32 *)&hwif->hwif_data);
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old = val = (u32)pci_get_drvdata(dev);
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if (drive->using_dma)
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val &= ~mask;
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else
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val |= mask;
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if (old != val) {
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pci_write_config_dword(dev, 0x40, val);
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*((u32 *)&hwif->hwif_data) = val;
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pci_set_drvdata(dev, (void *)val);
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}
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}
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@ -316,14 +316,13 @@ static void sl82c105_selectproc(ide_drive_t *drive)
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*/
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static void sl82c105_resetproc(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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u32 val;
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DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
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pci_read_config_dword(dev, 0x40, &val);
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*((u32 *)&hwif->hwif_data) = val;
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pci_set_drvdata(dev, (void *)val);
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}
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/*
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@ -394,6 +393,7 @@ static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const c
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pci_read_config_dword(dev, 0x40, &val);
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val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
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pci_write_config_dword(dev, 0x40, val);
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pci_set_drvdata(dev, (void *)val);
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return dev->irq;
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}
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@ -404,30 +404,25 @@ static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const c
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static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = hwif->pci_dev;
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unsigned int rev;
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u8 dma_state;
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u32 val;
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DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
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hwif->tuneproc = tune_sl82c105;
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hwif->selectproc = sl82c105_selectproc;
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hwif->resetproc = sl82c105_resetproc;
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/* Default to PIO 0 for fallback unless tuned otherwise,
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* we always autotune PIO, this is done before DMA is
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* checked, so there is no risk of accidentally disabling
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* DMA
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*/
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/*
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* Default to PIO 0 for fallback unless tuned otherwise.
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* We always autotune PIO, this is done before DMA is checked,
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* so there's no risk of accidentally disabling DMA
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*/
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hwif->drives[0].pio_speed = XFER_PIO_0;
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hwif->drives[0].autotune = 1;
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hwif->drives[1].pio_speed = XFER_PIO_1;
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hwif->drives[1].pio_speed = XFER_PIO_0;
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hwif->drives[1].autotune = 1;
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pci_read_config_dword(dev, 0x40, &val);
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*((u32 *)&hwif->hwif_data) = val;
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hwif->atapi_dma = 0;
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hwif->mwdma_mask = 0;
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hwif->swdma_mask = 0;
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