[MIPS] IP32: Fix build by conversion to irq_cpu.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Ralf Baechle
parent
65a6ec0d72
commit
dd67b1556e
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@ -410,6 +410,7 @@ config SGI_IP32
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select BOOT_ELF32
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select IRQ_CPU
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select R5000_CPU_SCACHE
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select RM7000_CPU_SCACHE
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select SYS_HAS_CPU_R5000
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@ -20,6 +20,7 @@
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#include <linux/random.h>
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#include <linux/sched.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/signal.h>
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#include <asm/system.h>
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@ -46,7 +47,8 @@ static void inline flush_mace_bus(void)
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#define DBG(x...)
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#endif
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/* O2 irq map
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/*
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* O2 irq map
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*
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* IP0 -> software (ignored)
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* IP1 -> software (ignored)
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@ -55,60 +57,60 @@ static void inline flush_mace_bus(void)
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* IP4 -> (irq2) X unknown
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* IP5 -> (irq3) X unknown
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* IP6 -> (irq4) X unknown
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* IP7 -> (irq5) 0 CPU count/compare timer (system timer)
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* IP7 -> (irq5) 7 CPU count/compare timer (system timer)
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*
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* crime: (C)
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*
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* CRIME_INT_STAT 31:0:
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*
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* 0 -> 1 Video in 1
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* 1 -> 2 Video in 2
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* 2 -> 3 Video out
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* 3 -> 4 Mace ethernet
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* 0 -> 8 Video in 1
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* 1 -> 9 Video in 2
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* 2 -> 10 Video out
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* 3 -> 11 Mace ethernet
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* 4 -> S SuperIO sub-interrupt
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* 5 -> M Miscellaneous sub-interrupt
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* 6 -> A Audio sub-interrupt
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* 7 -> 8 PCI bridge errors
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* 8 -> 9 PCI SCSI aic7xxx 0
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* 9 -> 10 PCI SCSI aic7xxx 1
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* 10 -> 11 PCI slot 0
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* 11 -> 12 unused (PCI slot 1)
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* 12 -> 13 unused (PCI slot 2)
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* 13 -> 14 unused (PCI shared 0)
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* 14 -> 15 unused (PCI shared 1)
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* 15 -> 16 unused (PCI shared 2)
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* 16 -> 17 GBE0 (E)
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* 17 -> 18 GBE1 (E)
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* 18 -> 19 GBE2 (E)
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* 19 -> 20 GBE3 (E)
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* 20 -> 21 CPU errors
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* 21 -> 22 Memory errors
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* 22 -> 23 RE empty edge (E)
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* 23 -> 24 RE full edge (E)
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* 24 -> 25 RE idle edge (E)
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* 25 -> 26 RE empty level
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* 26 -> 27 RE full level
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* 27 -> 28 RE idle level
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* 28 -> 29 unused (software 0) (E)
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* 29 -> 30 unused (software 1) (E)
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* 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
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* 31 -> 32 VICE
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* 7 -> 15 PCI bridge errors
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* 8 -> 16 PCI SCSI aic7xxx 0
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* 9 -> 17 PCI SCSI aic7xxx 1
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* 10 -> 18 PCI slot 0
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* 11 -> 19 unused (PCI slot 1)
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* 12 -> 20 unused (PCI slot 2)
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* 13 -> 21 unused (PCI shared 0)
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* 14 -> 22 unused (PCI shared 1)
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* 15 -> 23 unused (PCI shared 2)
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* 16 -> 24 GBE0 (E)
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* 17 -> 25 GBE1 (E)
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* 18 -> 26 GBE2 (E)
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* 19 -> 27 GBE3 (E)
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* 20 -> 28 CPU errors
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* 21 -> 29 Memory errors
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* 22 -> 30 RE empty edge (E)
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* 23 -> 31 RE full edge (E)
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* 24 -> 32 RE idle edge (E)
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* 25 -> 33 RE empty level
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* 26 -> 34 RE full level
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* 27 -> 35 RE idle level
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* 28 -> 36 unused (software 0) (E)
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* 29 -> 37 unused (software 1) (E)
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* 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
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* 31 -> 39 VICE
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*
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* S, M, A: Use the MACE ISA interrupt register
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* MACE_ISA_INT_STAT 31:0
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*
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* 0-7 -> 33-40 Audio
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* 8 -> 41 RTC
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* 9 -> 42 Keyboard
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* 0-7 -> 40-47 Audio
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* 8 -> 48 RTC
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* 9 -> 49 Keyboard
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* 10 -> X Keyboard polled
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* 11 -> 44 Mouse
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* 11 -> 51 Mouse
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* 12 -> X Mouse polled
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* 13-15 -> 46-48 Count/compare timers
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* 16-19 -> 49-52 Parallel (16 E)
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* 20-25 -> 53-58 Serial 1 (22 E)
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* 26-31 -> 59-64 Serial 2 (28 E)
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* 13-15 -> 53-55 Count/compare timers
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* 16-19 -> 56-59 Parallel (16 E)
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* 20-25 -> 60-62 Serial 1 (22 E)
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* 26-31 -> 66-71 Serial 2 (28 E)
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*
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* Note that this means IRQs 5-7, 43, and 45 do not exist. This is a
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* Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
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* different IRQ map than IRIX uses, but that's OK as Linux irq handling
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* is quite different anyway.
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*/
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@ -130,36 +132,6 @@ struct irqaction cpuerr_irq = {
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.name = "CRIME CPU error",
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};
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/*
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* For interrupts wired from a single device to the CPU. Only the clock
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* uses this it seems, which is IRQ 0 and IP7.
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*/
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static void enable_cpu_irq(unsigned int irq)
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{
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set_c0_status(STATUSF_IP7);
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}
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static void disable_cpu_irq(unsigned int irq)
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{
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clear_c0_status(STATUSF_IP7);
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}
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static void end_cpu_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_cpu_irq(irq);
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}
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static struct irq_chip ip32_cpu_interrupt = {
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.name = "IP32 CPU",
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.ack = disable_cpu_irq,
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.mask = disable_cpu_irq,
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.mask_ack = disable_cpu_irq,
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.unmask = enable_cpu_irq,
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.end = end_cpu_irq,
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};
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/*
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* This is for pure CRIME interrupts - ie not MACE. The advantage?
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* We get to split the register in half and do faster lookups.
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@ -422,15 +394,23 @@ static void ip32_irq0(void)
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uint64_t crime_int;
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int irq = 0;
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/*
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* Sanity check interrupt numbering enum.
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* MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
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* chained.
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*/
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BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
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BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
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crime_int = crime->istat & crime_mask;
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irq = __ffs(crime_int);
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irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
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crime_int = 1 << irq;
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if (crime_int & CRIME_MACEISA_INT_MASK) {
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unsigned long mace_int = mace->perif.ctrl.istat;
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irq = __ffs(mace_int & maceisa_mask) + 32;
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irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
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}
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irq++;
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DBG("*irq %u*\n", irq);
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do_IRQ(irq);
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}
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@ -457,7 +437,7 @@ static void ip32_irq4(void)
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static void ip32_irq5(void)
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{
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do_IRQ(IP32_R4K_TIMER_IRQ);
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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}
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asmlinkage void plat_irq_dispatch(void)
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@ -490,21 +470,25 @@ void __init arch_init_irq(void)
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mace->perif.ctrl.istat = 0;
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mace->perif.ctrl.imask = 0;
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for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
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struct irq_chip *controller;
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mips_cpu_irq_init();
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for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) {
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struct irq_chip *chip;
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if (irq == IP32_R4K_TIMER_IRQ)
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controller = &ip32_cpu_interrupt;
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else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
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controller = &ip32_mace_interrupt;
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else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
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controller = &ip32_macepci_interrupt;
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else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
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controller = &ip32_crime_interrupt;
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else
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controller = &ip32_maceisa_interrupt;
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switch (irq) {
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case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
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chip = &ip32_mace_interrupt;
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break;
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case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
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chip = &ip32_macepci_interrupt;
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break;
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case CRIME_GBE0_IRQ ... CRIME_VICE_IRQ:
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chip = &ip32_crime_interrupt;
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break;
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default:
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chip = &ip32_maceisa_interrupt;
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}
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set_irq_chip(irq, controller);
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set_irq_chip(irq, chip);
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}
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setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
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setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
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@ -83,7 +83,7 @@ void __init plat_time_init(void)
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void __init plat_timer_setup(struct irqaction *irq)
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{
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irq->handler = no_action;
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setup_irq(IP32_R4K_TIMER_IRQ, irq);
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setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
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}
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void __init plat_mem_setup(void)
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@ -9,86 +9,104 @@
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#ifndef __ASM_IP32_INTS_H
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#define __ASM_IP32_INTS_H
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#include <asm/irq.h>
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/*
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* This list reflects the assignment of interrupt numbers to
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* interrupting events. Order is fairly irrelevant to handling
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* priority. This differs from irix.
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*/
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/* CPU */
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#define IP32_R4K_TIMER_IRQ 0
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enum ip32_irq_no {
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/*
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* CPU interrupts are 0 ... 7
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*/
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/* MACE */
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#define MACE_VID_IN1_IRQ 1
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#define MACE_VID_IN2_IRQ 2
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#define MACE_VID_OUT_IRQ 3
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#define MACE_ETHERNET_IRQ 4
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/* SUPERIO, MISC, and AUDIO are MACEISA */
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#define MACE_PCI_BRIDGE_IRQ 8
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/*
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* MACE
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*/
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MACE_VID_IN1_IRQ = MIPS_CPU_IRQ_BASE + 8,
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MACE_VID_IN2_IRQ,
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MACE_VID_OUT_IRQ,
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MACE_ETHERNET_IRQ,
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/* SUPERIO, MISC, and AUDIO are MACEISA */
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__MACE_SUPERIO,
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__MACE_MISC,
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__MACE_AUDIO,
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MACE_PCI_BRIDGE_IRQ,
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/* MACEPCI */
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#define MACEPCI_SCSI0_IRQ 9
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#define MACEPCI_SCSI1_IRQ 10
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#define MACEPCI_SLOT0_IRQ 11
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#define MACEPCI_SLOT1_IRQ 12
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#define MACEPCI_SLOT2_IRQ 13
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#define MACEPCI_SHARED0_IRQ 14
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#define MACEPCI_SHARED1_IRQ 15
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#define MACEPCI_SHARED2_IRQ 16
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/*
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* MACEPCI
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*/
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MACEPCI_SCSI0_IRQ,
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MACEPCI_SCSI1_IRQ,
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MACEPCI_SLOT0_IRQ,
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MACEPCI_SLOT1_IRQ,
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MACEPCI_SLOT2_IRQ,
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MACEPCI_SHARED0_IRQ,
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MACEPCI_SHARED1_IRQ,
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MACEPCI_SHARED2_IRQ,
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/* CRIME */
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#define CRIME_GBE0_IRQ 17
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#define CRIME_GBE1_IRQ 18
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#define CRIME_GBE2_IRQ 19
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#define CRIME_GBE3_IRQ 20
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#define CRIME_CPUERR_IRQ 21
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#define CRIME_MEMERR_IRQ 22
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#define CRIME_RE_EMPTY_E_IRQ 23
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#define CRIME_RE_FULL_E_IRQ 24
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#define CRIME_RE_IDLE_E_IRQ 25
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#define CRIME_RE_EMPTY_L_IRQ 26
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#define CRIME_RE_FULL_L_IRQ 27
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#define CRIME_RE_IDLE_L_IRQ 28
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#define CRIME_SOFT0_IRQ 29
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#define CRIME_SOFT1_IRQ 30
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#define CRIME_SOFT2_IRQ 31
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#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ
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#define CRIME_VICE_IRQ 32
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/*
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* CRIME
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*/
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CRIME_GBE0_IRQ,
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CRIME_GBE1_IRQ,
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CRIME_GBE2_IRQ,
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CRIME_GBE3_IRQ,
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CRIME_CPUERR_IRQ,
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CRIME_MEMERR_IRQ,
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CRIME_RE_EMPTY_E_IRQ,
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CRIME_RE_FULL_E_IRQ,
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CRIME_RE_IDLE_E_IRQ,
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CRIME_RE_EMPTY_L_IRQ,
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CRIME_RE_FULL_L_IRQ,
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CRIME_RE_IDLE_L_IRQ,
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CRIME_SOFT0_IRQ,
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CRIME_SOFT1_IRQ,
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CRIME_SOFT2_IRQ,
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CRIME_SYSCORERR_IRQ = CRIME_SOFT2_IRQ,
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CRIME_VICE_IRQ,
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/* MACEISA */
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#define MACEISA_AUDIO_SW_IRQ 33
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#define MACEISA_AUDIO_SC_IRQ 34
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#define MACEISA_AUDIO1_DMAT_IRQ 35
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#define MACEISA_AUDIO1_OF_IRQ 36
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#define MACEISA_AUDIO2_DMAT_IRQ 37
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#define MACEISA_AUDIO2_MERR_IRQ 38
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#define MACEISA_AUDIO3_DMAT_IRQ 39
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#define MACEISA_AUDIO3_MERR_IRQ 40
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#define MACEISA_RTC_IRQ 41
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#define MACEISA_KEYB_IRQ 42
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/* MACEISA_KEYB_POLL is not an IRQ */
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#define MACEISA_MOUSE_IRQ 44
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/* MACEISA_MOUSE_POLL is not an IRQ */
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#define MACEISA_TIMER0_IRQ 46
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#define MACEISA_TIMER1_IRQ 47
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#define MACEISA_TIMER2_IRQ 48
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#define MACEISA_PARALLEL_IRQ 49
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#define MACEISA_PAR_CTXA_IRQ 50
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#define MACEISA_PAR_CTXB_IRQ 51
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#define MACEISA_PAR_MERR_IRQ 52
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#define MACEISA_SERIAL1_IRQ 53
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#define MACEISA_SERIAL1_TDMAT_IRQ 54
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#define MACEISA_SERIAL1_TDMAPR_IRQ 55
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#define MACEISA_SERIAL1_TDMAME_IRQ 56
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#define MACEISA_SERIAL1_RDMAT_IRQ 57
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#define MACEISA_SERIAL1_RDMAOR_IRQ 58
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#define MACEISA_SERIAL2_IRQ 59
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#define MACEISA_SERIAL2_TDMAT_IRQ 60
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#define MACEISA_SERIAL2_TDMAPR_IRQ 61
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#define MACEISA_SERIAL2_TDMAME_IRQ 62
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#define MACEISA_SERIAL2_RDMAT_IRQ 63
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#define MACEISA_SERIAL2_RDMAOR_IRQ 64
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/*
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* MACEISA
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*/
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MACEISA_AUDIO_SW_IRQ,
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MACEISA_AUDIO_SC_IRQ,
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MACEISA_AUDIO1_DMAT_IRQ,
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MACEISA_AUDIO1_OF_IRQ,
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MACEISA_AUDIO2_DMAT_IRQ,
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MACEISA_AUDIO2_MERR_IRQ,
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MACEISA_AUDIO3_DMAT_IRQ,
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MACEISA_AUDIO3_MERR_IRQ,
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MACEISA_RTC_IRQ,
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MACEISA_KEYB_IRQ,
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/* MACEISA_KEYB_POLL is not an IRQ */
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__MACEISA_KEYB_POLL,
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MACEISA_MOUSE_IRQ,
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/* MACEISA_MOUSE_POLL is not an IRQ */
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__MACEISA_MOUSE_POLL,
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MACEISA_TIMER0_IRQ,
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MACEISA_TIMER1_IRQ,
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MACEISA_TIMER2_IRQ,
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MACEISA_PARALLEL_IRQ,
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MACEISA_PAR_CTXA_IRQ,
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MACEISA_PAR_CTXB_IRQ,
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MACEISA_PAR_MERR_IRQ,
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MACEISA_SERIAL1_IRQ,
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MACEISA_SERIAL1_TDMAT_IRQ,
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MACEISA_SERIAL1_TDMAPR_IRQ,
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MACEISA_SERIAL1_TDMAME_IRQ,
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MACEISA_SERIAL1_RDMAT_IRQ,
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MACEISA_SERIAL1_RDMAOR_IRQ,
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MACEISA_SERIAL2_IRQ,
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MACEISA_SERIAL2_TDMAT_IRQ,
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MACEISA_SERIAL2_TDMAPR_IRQ,
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MACEISA_SERIAL2_TDMAME_IRQ,
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MACEISA_SERIAL2_RDMAT_IRQ,
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MACEISA_SERIAL2_RDMAOR_IRQ,
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#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ
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IP32_IRQ_MAX = MACEISA_SERIAL2_RDMAOR_IRQ
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};
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#endif /* __ASM_IP32_INTS_H */
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