ARM: 5959/1: ARM: perf-events: request PMU interrupts with IRQF_NOBALANCING
If IRQ balancing is used on a multicore ARM system, PMU interrupt lines may be relocated onto CPUs other than the one causing the counter overflow. This can result in misattribution of events to the wrong core and, in the case that the CPU handling the interrupt has not experience counter overflow, the interrupt can be disabled because the handler returns IRQ_NONE. This patch adds the IRQF_NOBALANCING flag to the request_irq call in perf_events.c. Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -332,7 +332,8 @@ armpmu_reserve_hardware(void)
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for (i = 0; i < pmu_irqs->num_irqs; ++i) {
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err = request_irq(pmu_irqs->irqs[i], armpmu->handle_irq,
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IRQF_DISABLED, "armpmu", NULL);
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IRQF_DISABLED | IRQF_NOBALANCING,
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"armpmu", NULL);
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if (err) {
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pr_warning("unable to request IRQ%d for ARM "
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"perf counters\n", pmu_irqs->irqs[i]);
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