Delete regulator-compatible usage in mt8135-evbp1.dts.
The regualtor-compatible binding is deprecated, instead the node name is used. Mediatek timer driver supports as well mt8127, mt8135 and mt8173. Add these SOCs to the bindings list. Power domains venc and venc_lt need clocks two extra clocks to access their registers. We update the bindings documentation about this. Update SMP bindings documentation by adding support for mt6589 and mt81xx SOCs. Update mt8127.dtsi and mt8135.dtsi to enable SMP support. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWI4nIAAoJELQ5Ylss8dNDznQQAK9O/IgeKz069P+UT/HxnflC K21RbkMX5KKej8QS23yqYxZVz+c2HyZLpYF5sAl/k9p5oMsm1EvfNVfDC7acWmfM CY65ZgNOPixi9Yrd29qgN0IMtTzsQtMnS7dhiKloyZr9sszuRw0SHeAQOOjGFv2H rZ+N7fbH3RH6vDeWIurVY8bNppu3FJNeIFm6xbotiXcQvsXX8hJjoN6E8BI7Rzg+ i/p80IEmGRFvxHebZjrRCgVFIdqIfo0M02kxNVc4erH+Z7mLOmHZuYXIg7S3825M E5W+mJd6fqNh62qbPZUi2/0Y9TAsOPiIpxU+QDp2cBO37nse2/MeWPhJyg6DfCO/ RuC0Y+tJx1fxF+5+/7lkXeWqsvzo5twJTGcLu+D0pPSTVb5Gy0P9671QMJPBknf+ 6zy4qqjSYNpsIz+OqbwlZHeQJEuDjt/DEVWqFmvW3DoUr5O8hRjHpFa4lJ6F084u tvSkSOuiJKtO1htAZLeVmMQOYylAPxpxKTc1AqIcLIiBkgkNKhz7v43vtdwETNIv 8qkJVNKGF8WNDdskM2/GamlC2hTabw8kMoPxeYtqzZz5BYBALeOND0TvclEMecnh nDzdTwlhJDdHOlT5hQ7ur9UecakFQSMzQnoJ35LbjU+lVKXOyFIphXuBAmlX7Fvi hgbvHY7WClquwgKJ+PUF =Lj7i -----END PGP SIGNATURE----- Merge tag 'v4.3-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt Delete regulator-compatible usage in mt8135-evbp1.dts. The regualtor-compatible binding is deprecated, instead the node name is used. Mediatek timer driver supports as well mt8127, mt8135 and mt8173. Add these SOCs to the bindings list. Power domains venc and venc_lt need clocks two extra clocks to access their registers. We update the bindings documentation about this. Update SMP bindings documentation by adding support for mt6589 and mt81xx SOCs. Update mt8127.dtsi and mt8135.dtsi to enable SMP support. * tag 'v4.3-next-dts' of https://github.com/mbgg/linux-mediatek: ARM: dts: mt8127: enable basic SMP bringup for mt8127 ARM: dts: mt8135: enable basic SMP bringup for mt8135 devicetree: bindings: add new SMP enable method Mediatek SoC dt-bindings: soc: Add clocks for Mediatek SCPSYS unit dt-bindings: add more MediaTek SoC to mtk-timer binding ARM: dts: mt8135-evbp1: remove regulator-compatible usage Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
de0b2a545c
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@ -195,6 +195,8 @@ nodes to be present and contain the properties described below.
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"marvell,armada-380-smp"
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"marvell,armada-390-smp"
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"marvell,armada-xp-smp"
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"mediatek,mt6589-smp"
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"mediatek,mt81xx-tz-smp"
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v2"
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@ -17,9 +17,9 @@ Required properties:
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- reg: Address range of the SCPSYS unit
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- infracfg: must contain a phandle to the infracfg controller
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- clock, clock-names: clocks according to the common clock binding.
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The clocks needed "mm" and "mfg". These are the
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clocks which hardware needs to be enabled before
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enabling certain power domains.
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The clocks needed "mm", "mfg", "venc" and "venc_lt".
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These are the clocks which hardware needs to be enabled
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before enabling certain power domains.
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Example:
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@ -30,7 +30,9 @@ Example:
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infracfg = <&infracfg>;
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clocks = <&clk26m>,
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<&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mfg", "mm";
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<&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "mfg", "mm", "venc", "venc_lt";
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};
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Example consumer:
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@ -3,10 +3,12 @@ Mediatek MT6577, MT6572 and MT6589 Timers
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Required properties:
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- compatible should contain:
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* "mediatek,mt6589-timer" for MT6589 compatible timers
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* "mediatek,mt6580-timer" for MT6580 compatible timers
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* "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580,
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MT6577)
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* "mediatek,mt6589-timer" for MT6589 compatible timers
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* "mediatek,mt8127-timer" for MT8127 compatible timers
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* "mediatek,mt8135-timer" for MT8135 compatible timers
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* "mediatek,mt8173-timer" for MT8173 compatible timers
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* "mediatek,mt6577-timer" for MT6577 and all above compatible timers
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- reg: Should contain location and length for timers register.
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- clocks: Clocks driving the timer hardware. This list should include two
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clocks. The order is system clock and as second clock the RTC clock.
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@ -23,6 +23,7 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt81xx-tz-smp";
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cpu@0 {
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device_type = "cpu";
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@ -47,6 +48,17 @@
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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trustzone-bootinfo@80002000 {
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compatible = "mediatek,trustzone-bootinfo";
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reg = <0 0x80002000 0 0x1000>;
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};
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -72,6 +84,21 @@
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <13000000>;
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arm,cpu-registers-not-fw-configured;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -32,7 +32,6 @@
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compatible = "mediatek,mt6397-regulator";
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mt6397_vpca15_reg: buck_vpca15 {
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regulator-compatible = "buck_vpca15";
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regulator-name = "vpca15";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1350000>;
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@ -41,7 +40,6 @@
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};
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mt6397_vpca7_reg: buck_vpca7 {
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regulator-compatible = "buck_vpca7";
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regulator-name = "vpca7";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1350000>;
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@ -50,7 +48,6 @@
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};
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mt6397_vsramca15_reg: buck_vsramca15 {
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regulator-compatible = "buck_vsramca15";
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regulator-name = "vsramca15";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1350000>;
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@ -59,7 +56,6 @@
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};
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mt6397_vsramca7_reg: buck_vsramca7 {
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regulator-compatible = "buck_vsramca7";
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regulator-name = "vsramca7";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1350000>;
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@ -68,7 +64,6 @@
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};
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mt6397_vcore_reg: buck_vcore {
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regulator-compatible = "buck_vcore";
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regulator-name = "vcore";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1350000>;
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@ -77,7 +72,6 @@
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};
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mt6397_vgpu_reg: buck_vgpu {
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regulator-compatible = "buck_vgpu";
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regulator-name = "vgpu";
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regulator-min-microvolt = < 700000>;
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regulator-max-microvolt = <1350000>;
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@ -86,7 +80,6 @@
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};
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mt6397_vdrm_reg: buck_vdrm {
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regulator-compatible = "buck_vdrm";
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regulator-name = "vdrm";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1400000>;
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@ -95,7 +88,6 @@
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};
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mt6397_vio18_reg: buck_vio18 {
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regulator-compatible = "buck_vio18";
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regulator-name = "vio18";
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regulator-min-microvolt = <1620000>;
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regulator-max-microvolt = <1980000>;
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@ -104,19 +96,16 @@
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};
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mt6397_vtcxo_reg: ldo_vtcxo {
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regulator-compatible = "ldo_vtcxo";
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regulator-name = "vtcxo";
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regulator-always-on;
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};
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mt6397_va28_reg: ldo_va28 {
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regulator-compatible = "ldo_va28";
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regulator-name = "va28";
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regulator-always-on;
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};
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mt6397_vcama_reg: ldo_vcama {
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regulator-compatible = "ldo_vcama";
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regulator-name = "vcama";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <2800000>;
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@ -124,18 +113,15 @@
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};
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mt6397_vio28_reg: ldo_vio28 {
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regulator-compatible = "ldo_vio28";
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regulator-name = "vio28";
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regulator-always-on;
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};
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mt6397_vusb_reg: ldo_vusb {
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regulator-compatible = "ldo_vusb";
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regulator-name = "vusb";
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};
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mt6397_vmc_reg: ldo_vmc {
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regulator-compatible = "ldo_vmc";
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regulator-name = "vmc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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@ -143,7 +129,6 @@
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};
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mt6397_vmch_reg: ldo_vmch {
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regulator-compatible = "ldo_vmch";
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regulator-name = "vmch";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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@ -151,7 +136,6 @@
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};
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mt6397_vemc_3v3_reg: ldo_vemc3v3 {
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regulator-compatible = "ldo_vemc3v3";
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regulator-name = "vemc_3v3";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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@ -159,7 +143,6 @@
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};
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mt6397_vgp1_reg: ldo_vgp1 {
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regulator-compatible = "ldo_vgp1";
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regulator-name = "vcamd";
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regulator-min-microvolt = <1220000>;
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regulator-max-microvolt = <3300000>;
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@ -167,7 +150,6 @@
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};
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mt6397_vgp2_reg: ldo_vgp2 {
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regulator-compatible = "ldo_vgp2";
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regulator-name = "vcamio";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3300000>;
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@ -175,7 +157,6 @@
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};
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mt6397_vgp3_reg: ldo_vgp3 {
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regulator-compatible = "ldo_vgp3";
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regulator-name = "vcamaf";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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@ -183,7 +164,6 @@
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};
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mt6397_vgp4_reg: ldo_vgp4 {
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regulator-compatible = "ldo_vgp4";
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regulator-name = "vgp4";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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@ -191,7 +171,6 @@
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};
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mt6397_vgp5_reg: ldo_vgp5 {
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regulator-compatible = "ldo_vgp5";
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regulator-name = "vgp5";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3000000>;
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@ -199,7 +178,6 @@
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};
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mt6397_vgp6_reg: ldo_vgp6 {
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regulator-compatible = "ldo_vgp6";
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regulator-name = "vgp6";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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@ -207,7 +185,6 @@
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};
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mt6397_vibr_reg: ldo_vibr {
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regulator-compatible = "ldo_vibr";
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regulator-name = "vibr";
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <3300000>;
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@ -46,6 +46,7 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt81xx-tz-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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@ -72,6 +73,17 @@
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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trustzone-bootinfo@80002000 {
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compatible = "mediatek,trustzone-bootinfo";
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reg = <0 0x80002000 0 0x1000>;
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};
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -97,6 +109,21 @@
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <13000000>;
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arm,cpu-registers-not-fw-configured;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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