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Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 

Jeff Kirsher says:

====================
1GbE Intel Wired LAN Driver Updates 2020-05-19

This series contains updates to igc only.

Sasha cleans up the igc driver code that is not used or needed.

Vitaly cleans up driver code that was used to support Virtualization on
a device that is not supported by igc, so remove the dead code.

Andre renames a few macros to align with register and field names
described in the data sheet.  Also adds the VLAN Priority Queue Fliter
and EType Queue Filter registers to the list of registers dumped by
igc_get_regs().  Added additional debug messages and updated return codes
for unsupported features.  Refactored the VLAN priority filtering code to
move the core logic into igc_main.c.  Cleaned up duplicate code and
useless code.
====================

Acked-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
alistair/sunxi64-5.8
David S. Miller 2020-05-20 19:27:57 -07:00
parent c536fc74b4 e5264212eb
commit de1b99ef2a
8 changed files with 184 additions and 163 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/net/ethernet/intel/igc/igc.h
View File

@ -26,7 +26,7 @@ void igc_set_ethtool_ops(struct net_device *);
#define MAX_Q_VECTORS 8
#define MAX_STD_JUMBO_FRAME_SIZE 9216
#define MAX_ETYPE_FILTER (4 - 1)
#define MAX_ETYPE_FILTER 8
#define IGC_RETA_SIZE 128
struct igc_tx_queue_stats {
@ -189,7 +189,6 @@ struct igc_adapter {
/* lock for RX network flow classification filter */
spinlock_t nfc_lock;
bool etype_bitmap[MAX_ETYPE_FILTER];
struct igc_mac_addr *mac_table;
@ -235,6 +234,11 @@ int igc_add_mac_filter(struct igc_adapter *adapter, const u8 *addr,
const s8 queue, const u8 flags);
int igc_del_mac_filter(struct igc_adapter *adapter, const u8 *addr,
const u8 flags);
int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio,
int queue);
void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio);
int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype, int queue);
int igc_del_etype_filter(struct igc_adapter *adapter, u16 etype);
void igc_update_stats(struct igc_adapter *adapter);
/* igc_dump declarations */
@ -463,7 +467,6 @@ struct igc_nfc_filter {
struct hlist_node nfc_node;
struct igc_nfc_input filter;
unsigned long cookie;
u16 etype_reg_index;
u16 sw_idx;
u16 action;
};

15
drivers/net/ethernet/intel/igc/igc_defines.h
View File

@ -163,11 +163,6 @@
/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
#define NVM_SUM 0xBABA
#define NVM_PBA_OFFSET_0 8
#define NVM_PBA_OFFSET_1 9
#define NVM_RESERVED_WORD 0xFFFF
#define NVM_PBA_PTR_GUARD 0xFAFA
#define NVM_WORD_SIZE_BASE_SHIFT 6
/* Collision related configuration parameters */
@ -249,7 +244,6 @@
/* Interrupt Cause Set */
#define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */
#define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */
#define IGC_ICS_DRSTA IGC_ICR_DRSTA /* Device Reset Aserted */
#define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
#define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
@ -389,9 +383,6 @@
#define IGC_TSICR_INTERRUPTS IGC_TSICR_TXTS
/* PTP Queue Filter */
#define IGC_ETQF_1588 BIT(30)
#define IGC_FTQF_VF_BP 0x00008000
#define IGC_FTQF_1588_TIME_STAMP 0x08000000
#define IGC_FTQF_MASK 0xF0000000
@ -513,9 +504,9 @@
#define IGC_MAX_MAC_HDR_LEN 127
#define IGC_MAX_NETWORK_HDR_LEN 511
#define IGC_VLAPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4))
#define IGC_VLAPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4))
#define IGC_VLAPQF_QUEUE_MASK 0x03
#define IGC_VLANPQF_QSEL(_n, q_idx) ((q_idx) << ((_n) * 4))
#define IGC_VLANPQF_VALID(_n) (0x1 << (3 + (_n) * 4))
#define IGC_VLANPQF_QUEUE_MASK 0x03
#define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
#define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type:1=IPv4 */

4
drivers/net/ethernet/intel/igc/igc_dump.c
View File

@ -35,10 +35,6 @@ static const struct igc_reg_info igc_reg_info_tbl[] = {
{IGC_TDH(0), "TDH"},
{IGC_TDT(0), "TDT"},
{IGC_TXDCTL(0), "TXDCTL"},
{IGC_TDFH, "TDFH"},
{IGC_TDFT, "TDFT"},
{IGC_TDFHS, "TDFHS"},
{IGC_TDFPC, "TDFPC"},
/* List Terminator */
{}

140
drivers/net/ethernet/intel/igc/igc_ethtool.c
View File

@ -316,6 +316,11 @@ static void igc_get_regs(struct net_device *netdev,
regs_buff[172 + i] = rd32(IGC_RAL(i));
for (i = 0; i < 16; i++)
regs_buff[188 + i] = rd32(IGC_RAH(i));
regs_buff[204] = rd32(IGC_VLANPQF);
for (i = 0; i < 8; i++)
regs_buff[205 + i] = rd32(IGC_ETQF(i));
}
static void igc_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
@ -1181,75 +1186,6 @@ static int igc_set_rss_hash_opt(struct igc_adapter *adapter,
return 0;
}
static int igc_rxnfc_write_etype_filter(struct igc_adapter *adapter,
struct igc_nfc_filter *input)
{
struct igc_hw *hw = &adapter->hw;
u8 i;
u32 etqf;
u16 etype;
/* find an empty etype filter register */
for (i = 0; i < MAX_ETYPE_FILTER; ++i) {
if (!adapter->etype_bitmap[i])
break;
}
if (i == MAX_ETYPE_FILTER) {
netdev_err(adapter->netdev,
"ethtool -N: etype filters are all used\n");
return -EINVAL;
}
adapter->etype_bitmap[i] = true;
etqf = rd32(IGC_ETQF(i));
etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK);
etqf |= IGC_ETQF_FILTER_ENABLE;
etqf &= ~IGC_ETQF_ETYPE_MASK;
etqf |= (etype & IGC_ETQF_ETYPE_MASK);
etqf &= ~IGC_ETQF_QUEUE_MASK;
etqf |= ((input->action << IGC_ETQF_QUEUE_SHIFT)
& IGC_ETQF_QUEUE_MASK);
etqf |= IGC_ETQF_QUEUE_ENABLE;
wr32(IGC_ETQF(i), etqf);
input->etype_reg_index = i;
return 0;
}
static int igc_rxnfc_write_vlan_prio_filter(struct igc_adapter *adapter,
struct igc_nfc_filter *input)
{
struct igc_hw *hw = &adapter->hw;
u8 vlan_priority;
u16 queue_index;
u32 vlapqf;
vlapqf = rd32(IGC_VLAPQF);
vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK)
>> VLAN_PRIO_SHIFT;
queue_index = (vlapqf >> (vlan_priority * 4)) & IGC_VLAPQF_QUEUE_MASK;
/* check whether this vlan prio is already set */
if (vlapqf & IGC_VLAPQF_P_VALID(vlan_priority) &&
queue_index != input->action) {
netdev_err(adapter->netdev,
"ethtool rxnfc set VLAN prio filter failed\n");
return -EEXIST;
}
vlapqf |= IGC_VLAPQF_P_VALID(vlan_priority);
vlapqf |= IGC_VLAPQF_QUEUE_SEL(vlan_priority, input->action);
wr32(IGC_VLAPQF, vlapqf);
return 0;
}
int igc_add_filter(struct igc_adapter *adapter, struct igc_nfc_filter *input)
{
struct igc_hw *hw = &adapter->hw;
@ -1263,7 +1199,9 @@ int igc_add_filter(struct igc_adapter *adapter, struct igc_nfc_filter *input)
}
if (input->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
err = igc_rxnfc_write_etype_filter(adapter, input);
u16 etype = ntohs(input->filter.etype);
err = igc_add_etype_filter(adapter, etype, input->action);
if (err)
return err;
}
@ -1283,53 +1221,30 @@ int igc_add_filter(struct igc_adapter *adapter, struct igc_nfc_filter *input)
return err;
}
if (input->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI)
err = igc_rxnfc_write_vlan_prio_filter(adapter, input);
if (input->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
int prio = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK) >>
VLAN_PRIO_SHIFT;
err = igc_add_vlan_prio_filter(adapter, prio, input->action);
if (err)
return err;
}
return err;
}
static void igc_clear_etype_filter_regs(struct igc_adapter *adapter,
u16 reg_index)
{
struct igc_hw *hw = &adapter->hw;
u32 etqf = rd32(IGC_ETQF(reg_index));
etqf &= ~IGC_ETQF_QUEUE_ENABLE;
etqf &= ~IGC_ETQF_QUEUE_MASK;
etqf &= ~IGC_ETQF_FILTER_ENABLE;
wr32(IGC_ETQF(reg_index), etqf);
adapter->etype_bitmap[reg_index] = false;
}
static void igc_clear_vlan_prio_filter(struct igc_adapter *adapter,
u16 vlan_tci)
{
struct igc_hw *hw = &adapter->hw;
u8 vlan_priority;
u32 vlapqf;
vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
vlapqf = rd32(IGC_VLAPQF);
vlapqf &= ~IGC_VLAPQF_P_VALID(vlan_priority);
vlapqf &= ~IGC_VLAPQF_QUEUE_SEL(vlan_priority,
IGC_VLAPQF_QUEUE_MASK);
wr32(IGC_VLAPQF, vlapqf);
return 0;
}
int igc_erase_filter(struct igc_adapter *adapter, struct igc_nfc_filter *input)
{
if (input->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE)
igc_clear_etype_filter_regs(adapter,
input->etype_reg_index);
if (input->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
u16 etype = ntohs(input->filter.etype);
if (input->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI)
igc_clear_vlan_prio_filter(adapter,
ntohs(input->filter.vlan_tci));
igc_del_etype_filter(adapter, etype);
}
if (input->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
int prio = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK) >>
VLAN_PRIO_SHIFT;
igc_del_vlan_prio_filter(adapter, prio);
}
if (input->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)
igc_del_mac_filter(adapter, input->filter.src_addr,
@ -1445,7 +1360,8 @@ static int igc_add_ethtool_nfc_entry(struct igc_adapter *adapter,
if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) {
if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {
err = -EINVAL;
netdev_dbg(netdev, "VLAN mask not supported\n");
err = -EOPNOTSUPP;
goto err_out;
}
input->filter.vlan_tci = fsp->h_ext.vlan_tci;

4
drivers/net/ethernet/intel/igc/igc_mac.h
View File

@ -8,10 +8,6 @@
#include "igc_phy.h"
#include "igc_defines.h"
#ifndef IGC_REMOVED
#define IGC_REMOVED(a) (0)
#endif /* IGC_REMOVED */
/* forward declaration */
s32 igc_disable_pcie_master(struct igc_hw *hw);
s32 igc_check_for_copper_link(struct igc_hw *hw);

148
drivers/net/ethernet/intel/igc/igc_main.c
View File

@ -2314,6 +2314,151 @@ int igc_del_mac_filter(struct igc_adapter *adapter, const u8 *addr,
return 0;
}
/**
* igc_add_vlan_prio_filter() - Add VLAN priority filter
* @adapter: Pointer to adapter where the filter should be added
* @prio: VLAN priority value
* @queue: Queue number which matching frames are assigned to
*
* Return: 0 in case of success, negative errno code otherwise.
*/
int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio, int queue)
{
struct net_device *dev = adapter->netdev;
struct igc_hw *hw = &adapter->hw;
u32 vlanpqf;
vlanpqf = rd32(IGC_VLANPQF);
if (vlanpqf & IGC_VLANPQF_VALID(prio)) {
netdev_dbg(dev, "VLAN priority filter already in use\n");
return -EEXIST;
}
vlanpqf |= IGC_VLANPQF_QSEL(prio, queue);
vlanpqf |= IGC_VLANPQF_VALID(prio);
wr32(IGC_VLANPQF, vlanpqf);
netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n",
prio, queue);
return 0;
}
/**
* igc_del_vlan_prio_filter() - Delete VLAN priority filter
* @adapter: Pointer to adapter where the filter should be deleted from
* @prio: VLAN priority value
*/
void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio)
{
struct igc_hw *hw = &adapter->hw;
u32 vlanpqf;
vlanpqf = rd32(IGC_VLANPQF);
vlanpqf &= ~IGC_VLANPQF_VALID(prio);
vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK);
wr32(IGC_VLANPQF, vlanpqf);
netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n",
prio);
}
static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter)
{
struct igc_hw *hw = &adapter->hw;
int i;
for (i = 0; i < MAX_ETYPE_FILTER; i++) {
u32 etqf = rd32(IGC_ETQF(i));
if (!(etqf & IGC_ETQF_FILTER_ENABLE))
return i;
}
return -1;
}
/**
* igc_add_etype_filter() - Add ethertype filter
* @adapter: Pointer to adapter where the filter should be added
* @etype: Ethertype value
* @queue: If non-negative, queue assignment feature is enabled and frames
* matching the filter are enqueued onto 'queue'. Otherwise, queue
* assignment is disabled.
*
* Return: 0 in case of success, negative errno code otherwise.
*/
int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype, int queue)
{
struct igc_hw *hw = &adapter->hw;
int index;
u32 etqf;
index = igc_get_avail_etype_filter_slot(adapter);
if (index < 0)
return -ENOSPC;
etqf = rd32(IGC_ETQF(index));
etqf &= ~IGC_ETQF_ETYPE_MASK;
etqf |= etype;
if (queue >= 0) {
etqf &= ~IGC_ETQF_QUEUE_MASK;
etqf |= (queue << IGC_ETQF_QUEUE_SHIFT);
etqf |= IGC_ETQF_QUEUE_ENABLE;
}
etqf |= IGC_ETQF_FILTER_ENABLE;
wr32(IGC_ETQF(index), etqf);
netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n",
etype, queue);
return 0;
}
static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype)
{
struct igc_hw *hw = &adapter->hw;
int i;
for (i = 0; i < MAX_ETYPE_FILTER; i++) {
u32 etqf = rd32(IGC_ETQF(i));
if ((etqf & IGC_ETQF_ETYPE_MASK) == etype)
return i;
}
return -1;
}
/**
* igc_del_etype_filter() - Delete ethertype filter
* @adapter: Pointer to adapter where the filter should be deleted from
* @etype: Ethertype value
*
* Return: 0 in case of success, negative errno code otherwise.
*/
int igc_del_etype_filter(struct igc_adapter *adapter, u16 etype)
{
struct igc_hw *hw = &adapter->hw;
int index;
index = igc_find_etype_filter(adapter, etype);
if (index < 0)
return -ENOENT;
wr32(IGC_ETQF(index), 0);
netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n",
etype);
return 0;
}
static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr)
{
struct igc_adapter *adapter = netdev_priv(netdev);
@ -4659,9 +4804,6 @@ u32 igc_rd32(struct igc_hw *hw, u32 reg)
u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
u32 value = 0;
if (IGC_REMOVED(hw_addr))
return ~value;
value = readl(&hw_addr[reg]);
/* reads should not return all F's */

12
drivers/net/ethernet/intel/igc/igc_ptp.c
View File

@ -305,7 +305,6 @@ static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
struct igc_hw *hw = &adapter->hw;
u32 tsync_rx_cfg = 0;
bool is_l4 = false;
bool is_l2 = false;
u32 regval;
/* reserved for future extensions */
@ -346,7 +345,6 @@ static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
tsync_rx_ctl |= IGC_TSYNCRXCTL_TYPE_EVENT_V2;
config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
is_l2 = true;
is_l4 = true;
break;
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
@ -370,7 +368,6 @@ static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
tsync_rx_ctl |= IGC_TSYNCRXCTL_TYPE_ALL;
tsync_rx_ctl |= IGC_TSYNCRXCTL_RXSYNSIG;
config->rx_filter = HWTSTAMP_FILTER_ALL;
is_l2 = true;
is_l4 = true;
if (hw->mac.type == igc_i225) {
@ -405,15 +402,6 @@ static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
/* define which PTP packets are time stamped */
wr32(IGC_TSYNCRXCFG, tsync_rx_cfg);
/* define ethertype filter for timestamped packets */
if (is_l2)
wr32(IGC_ETQF(3),
(IGC_ETQF_FILTER_ENABLE | /* enable filter */
IGC_ETQF_1588 | /* enable timestamping */
ETH_P_1588)); /* 1588 eth protocol type */
else
wr32(IGC_ETQF(3), 0);
/* L4 Queue Filter[3]: filter by destination port and protocol */
if (is_l4) {
u32 ftqf = (IPPROTO_UDP /* UDP */

15
drivers/net/ethernet/intel/igc/igc_regs.h
View File

@ -17,11 +17,6 @@
/* Internal Packet Buffer Size Registers */
#define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
#define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
#define IGC_TDFH 0x03410 /* Tx Data FIFO Head - RW */
#define IGC_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
#define IGC_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
#define IGC_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
#define IGC_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
/* NVM Register Descriptions */
#define IGC_EERD 0x12014 /* EEprom mode read - RW */
@ -36,9 +31,6 @@
#define IGC_FCRTH 0x02168 /* FC Receive Threshold High - RW */
#define IGC_FCRTV 0x02460 /* FC Refresh Timer Value - RW */
/* PCIe Register Description */
#define IGC_GCR 0x05B00 /* PCIe control- RW */
/* Semaphore registers */
#define IGC_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
#define IGC_SWSM 0x05B50 /* SW Semaphore */
@ -123,7 +115,7 @@
#define IGC_UTA 0x0A000 /* Unicast Table Array - RW */
#define IGC_RAL(_n) (0x05400 + ((_n) * 0x08))
#define IGC_RAH(_n) (0x05404 + ((_n) * 0x08))
#define IGC_VLAPQF 0x055B0 /* VLAN Priority Queue Filter VLAPQF */
#define IGC_VLANPQF 0x055B0 /* VLAN Priority Queue Filter - RW */
/* Transmit Register Descriptions */
#define IGC_TCTL 0x00400 /* Tx Control - RW */
@ -230,8 +222,6 @@
#define IGC_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
#define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
/* Transmit Scheduling Registers */
#define IGC_TQAVCTRL 0x3570
#define IGC_TXQCTL(_n) (0x3344 + 0x4 * (_n))
@ -278,8 +268,7 @@ u32 igc_rd32(struct igc_hw *hw, u32 reg);
#define wr32(reg, val) \
do { \
u8 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \
if (!IGC_REMOVED(hw_addr)) \
writel((val), &hw_addr[(reg)]); \
writel((val), &hw_addr[(reg)]); \
} while (0)
#define rd32(reg) (igc_rd32(hw, reg))