mmc: sdhci-esdhc-imx: add DDR mode support for mx6
When DDR mode is enabled, the initial pre_div should be 2. And the pre_div value should be changed accordingly from ... 02h) Base clock divided by 4 01h) Base clock divided by 2 00h) Base clock divided by 1 to .. 02h) Base clock divided by 8 01h) Base clock divided by 4 00h) Base clock divided by 2 Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -38,6 +38,7 @@
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#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
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#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
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#define ESDHC_WTMK_LVL 0x44
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#define ESDHC_WTMK_LVL 0x44
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#define ESDHC_MIX_CTRL 0x48
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#define ESDHC_MIX_CTRL 0x48
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#define ESDHC_MIX_CTRL_DDREN (1 << 3)
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#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
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#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
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#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
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#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
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#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
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#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
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@ -152,6 +153,7 @@ struct pltfm_imx_data {
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WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
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WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
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} multiblock_status;
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} multiblock_status;
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u32 uhs_mode;
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u32 uhs_mode;
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u32 is_ddr;
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};
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};
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static struct platform_device_id imx_esdhc_devtype[] = {
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static struct platform_device_id imx_esdhc_devtype[] = {
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@ -537,8 +539,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
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* The reset on usdhc fails to clear MIX_CTRL register.
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* The reset on usdhc fails to clear MIX_CTRL register.
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* Do it manually here.
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* Do it manually here.
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*/
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*/
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if (esdhc_is_usdhc(imx_data))
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if (esdhc_is_usdhc(imx_data)) {
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writel(0, host->ioaddr + ESDHC_MIX_CTRL);
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writel(0, host->ioaddr + ESDHC_MIX_CTRL);
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imx_data->is_ddr = 0;
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}
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}
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}
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}
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}
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@ -582,7 +586,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
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goto out;
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goto out;
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}
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}
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if (esdhc_is_usdhc(imx_data))
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if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
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pre_div = 1;
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pre_div = 1;
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temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
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temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
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@ -600,6 +604,9 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
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dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
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dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
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clock, host->mmc->actual_clock);
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clock, host->mmc->actual_clock);
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if (imx_data->is_ddr)
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pre_div >>= 2;
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else
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pre_div >>= 1;
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pre_div >>= 1;
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div--;
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div--;
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@ -826,6 +833,10 @@ static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
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break;
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break;
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_UHS_DDR50:
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imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50;
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imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50;
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writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
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ESDHC_MIX_CTRL_DDREN,
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host->ioaddr + ESDHC_MIX_CTRL);
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imx_data->is_ddr = 1;
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break;
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break;
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}
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}
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