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staging: sm750fb: Edit CamelCase in local variables 

Edit CamelCase in local variables across 4 files:
- sm750fb/ddk750_chip.c
- sm750fb/ddk750_chip.h
- sm750fb/ddk750_dvi.c
- sm750fb/ddk750_sii164.c
to comply with the coding style. Also edit associated comments
accordingly.
Issue found with Checkpatch.

Signed-off-by: Nishka Dasgupta <nishka.dasgupta@yahoo.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
hifive-unleashed-5.2
Nishka Dasgupta 2019-03-11 00:08:36 +05:30 committed by Greg Kroah-Hartman
parent 256ab3efbe
commit de5e4aea88
4 changed files with 86 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/staging/sm750fb/ddk750_chip.c
View File

@ -15,14 +15,14 @@ enum logical_chip_type sm750_get_chip_type(void)
return chip;
}
void sm750_set_chip_type(unsigned short devId, u8 revId)
void sm750_set_chip_type(unsigned short dev_id, u8 rev_id)
{
if (devId == 0x718) {
if (dev_id == 0x718) {
chip = SM718;
} else if (devId == 0x750) {
} else if (dev_id == 0x750) {
chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */
if (revId == SM750LE_REVISION_ID) {
if (rev_id == SM750LE_REVISION_ID) {
chip = SM750LE;
pr_info("found sm750le\n");
}
@ -321,7 +321,7 @@ unsigned int sm750_calc_pll_value(unsigned int request_orig,
int mini_diff;
unsigned int RN, quo, rem, fl_quo;
unsigned int input, request;
unsigned int tmpClock, ret;
unsigned int tmp_clock, ret;
const int max_OD = 3;
int max_d = 6;
@ -365,8 +365,8 @@ unsigned int sm750_calc_pll_value(unsigned int request_orig,
if (M < 256 && M > 0) {
unsigned int diff;
tmpClock = pll->inputFreq * M / N / X;
diff = abs(tmpClock - request_orig);
tmp_clock = pll->inputFreq * M / N / X;
diff = abs(tmp_clock - request_orig);
if (diff < mini_diff) {
pll->M = M;
pll->N = N;
@ -375,7 +375,7 @@ unsigned int sm750_calc_pll_value(unsigned int request_orig,
pll->POD = d - max_OD;
pll->OD = d - pll->POD;
mini_diff = diff;
ret = tmpClock;
ret = tmp_clock;
}
}
}

2
drivers/staging/sm750fb/ddk750_chip.h
View File

@ -93,7 +93,7 @@ struct initchip_param {
};
enum logical_chip_type sm750_get_chip_type(void);
void sm750_set_chip_type(unsigned short devId, u8 revId);
void sm750_set_chip_type(unsigned short dev_id, u8 rev_id);
unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
unsigned int sm750_format_pll_reg(struct pll_value *pPLL);
unsigned int ddk750_get_vm_size(void);

40
drivers/staging/sm750fb/ddk750_dvi.c
View File

@ -30,31 +30,31 @@ static struct dvi_ctrl_device g_dcftSupportedDviController[] = {
#endif
};
int dviInit(unsigned char edgeSelect,
unsigned char busSelect,
unsigned char dualEdgeClkSelect,
unsigned char hsyncEnable,
unsigned char vsyncEnable,
unsigned char deskewEnable,
unsigned char deskewSetting,
unsigned char continuousSyncEnable,
unsigned char pllFilterEnable,
unsigned char pllFilterValue)
int dviInit(unsigned char edge_select,
unsigned char bus_select,
unsigned char dual_edge_clk_select,
unsigned char hsync_enable,
unsigned char vsync_enable,
unsigned char deskew_enable,
unsigned char deskew_setting,
unsigned char continuous_sync_enable,
unsigned char pll_filter_enable,
unsigned char pll_filter_value)
{
struct dvi_ctrl_device *pCurrentDviCtrl;
pCurrentDviCtrl = g_dcftSupportedDviController;
if (pCurrentDviCtrl->pfnInit) {
return pCurrentDviCtrl->pfnInit(edgeSelect,
busSelect,
dualEdgeClkSelect,
hsyncEnable,
vsyncEnable,
deskewEnable,
deskewSetting,
continuousSyncEnable,
pllFilterEnable,
pllFilterValue);
return pCurrentDviCtrl->pfnInit(edge_select,
bus_select,
dual_edge_clk_select,
hsync_enable,
vsync_enable,
deskew_enable,
deskew_setting,
continuous_sync_enable,
pll_filter_enable,
pll_filter_value);
}
return -1; /* error */
}

114
drivers/staging/sm750fb/ddk750_sii164.c
View File

@ -69,58 +69,58 @@ unsigned short sii164GetDeviceID(void)
* This function initialize and detect the DVI controller chip.
*
* Input:
* edgeSelect - Edge Select:
* 0 = Input data is falling edge latched (falling edge
* latched first in dual edge mode)
* 1 = Input data is rising edge latched (rising edge
* latched first in dual edge mode)
* busSelect - Input Bus Select:
* 0 = Input data bus is 12-bits wide
* 1 = Input data bus is 24-bits wide
* dualEdgeClkSelect - Dual Edge Clock Select
* 0 = Input data is single edge latched
* 1 = Input data is dual edge latched
* hsyncEnable - Horizontal Sync Enable:
* 0 = HSYNC input is transmitted as fixed LOW
* 1 = HSYNC input is transmitted as is
* vsyncEnable - Vertical Sync Enable:
* 0 = VSYNC input is transmitted as fixed LOW
* 1 = VSYNC input is transmitted as is
* deskewEnable - De-skewing Enable:
* 0 = De-skew disabled
* 1 = De-skew enabled
* deskewSetting - De-skewing Setting (increment of 260psec)
* 0 = 1 step --> minimum setup / maximum hold
* 1 = 2 step
* 2 = 3 step
* 3 = 4 step
* 4 = 5 step
* 5 = 6 step
* 6 = 7 step
* 7 = 8 step --> maximum setup / minimum hold
* continuousSyncEnable- SYNC Continuous:
* 0 = Disable
* 1 = Enable
* pllFilterEnable - PLL Filter Enable
* 0 = Disable PLL Filter
* 1 = Enable PLL Filter
* pllFilterValue - PLL Filter characteristics:
* 0~7 (recommended value is 4)
* edge_select - Edge Select:
* 0 = Input data is falling edge latched (falling
* edge latched first in dual edge mode)
* 1 = Input data is rising edge latched (rising
* edge latched first in dual edge mode)
* bus_select - Input Bus Select:
* 0 = Input data bus is 12-bits wide
* 1 = Input data bus is 24-bits wide
* dual_edge_clk_select - Dual Edge Clock Select
* 0 = Input data is single edge latched
* 1 = Input data is dual edge latched
* hsync_enable - Horizontal Sync Enable:
* 0 = HSYNC input is transmitted as fixed LOW
* 1 = HSYNC input is transmitted as is
* vsync_enable - Vertical Sync Enable:
* 0 = VSYNC input is transmitted as fixed LOW
* 1 = VSYNC input is transmitted as is
* deskew_enable - De-skewing Enable:
* 0 = De-skew disabled
* 1 = De-skew enabled
* deskew_setting - De-skewing Setting (increment of 260psec)
* 0 = 1 step --> minimum setup / maximum hold
* 1 = 2 step
* 2 = 3 step
* 3 = 4 step
* 4 = 5 step
* 5 = 6 step
* 6 = 7 step
* 7 = 8 step --> maximum setup / minimum hold
* continuous_sync_enable- SYNC Continuous:
* 0 = Disable
* 1 = Enable
* pll_filter_enable - PLL Filter Enable
* 0 = Disable PLL Filter
* 1 = Enable PLL Filter
* pll_filter_value - PLL Filter characteristics:
* 0~7 (recommended value is 4)
*
* Output:
* 0 - Success
* -1 - Fail.
*/
long sii164InitChip(unsigned char edgeSelect,
unsigned char busSelect,
unsigned char dualEdgeClkSelect,
unsigned char hsyncEnable,
unsigned char vsyncEnable,
unsigned char deskewEnable,
unsigned char deskewSetting,
unsigned char continuousSyncEnable,
unsigned char pllFilterEnable,
unsigned char pllFilterValue)
long sii164InitChip(unsigned char edge_select,
unsigned char bus_select,
unsigned char dual_edge_clk_select,
unsigned char hsync_enable,
unsigned char vsync_enable,
unsigned char deskew_enable,
unsigned char deskew_setting,
unsigned char continuous_sync_enable,
unsigned char pll_filter_enable,
unsigned char pll_filter_value)
{
unsigned char config;
@ -139,31 +139,31 @@ long sii164InitChip(unsigned char edgeSelect,
*/
/* Select the edge */
if (edgeSelect == 0)
if (edge_select == 0)
config = SII164_CONFIGURATION_LATCH_FALLING;
else
config = SII164_CONFIGURATION_LATCH_RISING;
/* Select bus wide */
if (busSelect == 0)
if (bus_select == 0)
config |= SII164_CONFIGURATION_BUS_12BITS;
else
config |= SII164_CONFIGURATION_BUS_24BITS;
/* Select Dual/Single Edge Clock */
if (dualEdgeClkSelect == 0)
if (dual_edge_clk_select == 0)
config |= SII164_CONFIGURATION_CLOCK_SINGLE;
else
config |= SII164_CONFIGURATION_CLOCK_DUAL;
/* Select HSync Enable */
if (hsyncEnable == 0)
if (hsync_enable == 0)
config |= SII164_CONFIGURATION_HSYNC_FORCE_LOW;
else
config |= SII164_CONFIGURATION_HSYNC_AS_IS;
/* Select VSync Enable */
if (vsyncEnable == 0)
if (vsync_enable == 0)
config |= SII164_CONFIGURATION_VSYNC_FORCE_LOW;
else
config |= SII164_CONFIGURATION_VSYNC_AS_IS;
@ -175,12 +175,12 @@ long sii164InitChip(unsigned char edgeSelect,
* This fixes some artifacts problem in some mode on board 2.2.
* Somehow this fix does not affect board 2.1.
*/
if (deskewEnable == 0)
if (deskew_enable == 0)
config = SII164_DESKEW_DISABLE;
else
config = SII164_DESKEW_ENABLE;
switch (deskewSetting) {
switch (deskew_setting) {
case 0:
config |= SII164_DESKEW_1_STEP;
break;
@ -209,19 +209,19 @@ long sii164InitChip(unsigned char edgeSelect,
i2cWriteReg(SII164_I2C_ADDRESS, SII164_DESKEW, config);
/* Enable/Disable Continuous Sync. */
if (continuousSyncEnable == 0)
if (continuous_sync_enable == 0)
config = SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE;
else
config = SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE;
/* Enable/Disable PLL Filter */
if (pllFilterEnable == 0)
if (pll_filter_enable == 0)
config |= SII164_PLL_FILTER_DISABLE;
else
config |= SII164_PLL_FILTER_ENABLE;
/* Set the PLL Filter value */
config |= ((pllFilterValue & 0x07) << 1);
config |= ((pll_filter_value & 0x07) << 1);
i2cWriteReg(SII164_I2C_ADDRESS, SII164_PLL, config);