sh: clock-cpg div4 set_rate() shift fix
Make sure the div4 bitfield is shifted according to the enable_bit value in sh_clk_div4_set_rate(). Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -192,8 +192,8 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id
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return idx;
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value = __raw_readl(clk->enable_reg);
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value &= ~0xf;
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value |= idx;
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value &= ~(0xf << clk->enable_bit);
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value |= (idx << clk->enable_bit);
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__raw_writel(value, clk->enable_reg);
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return 0;
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