ARM: pm: only use preallocated page table during resume
Only use the preallocated page table during the resume, not while suspending. This avoids the overhead of having to switch unnecessarily to the resume page table in the suspend path. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Russell King
parent
e8ce0eb5e2
commit
de8e71ca4f
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@ -9,12 +9,14 @@
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/*
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* Save CPU state for a suspend
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* r0 = phys addr of temporary page tables
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* r1 = v:p offset
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* r2 = suspend function arg0
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* r3 = suspend function
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*/
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ENTRY(__cpu_suspend)
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stmfd sp!, {r4 - r11, lr}
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mov r4, r0
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#ifdef MULTI_CPU
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ldr r10, =processor
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ldr r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
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@ -27,7 +29,7 @@ ENTRY(__cpu_suspend)
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sub sp, sp, r5 @ allocate CPU state on stack
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mov r0, sp @ save pointer to CPU save block
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add ip, ip, r1 @ convert resume fn to phys
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stmfd sp!, {r6, ip} @ save virt SP, phys resume fn
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stmfd sp!, {r4, r6, ip} @ save phys pgd, virt SP, phys resume fn
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ldr r5, =sleep_save_sp
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add r6, sp, r1 @ convert SP to phys
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stmfd sp!, {r2, r3} @ save suspend func arg and pointer
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@ -60,7 +62,7 @@ ENDPROC(__cpu_suspend)
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.ltorg
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cpu_suspend_abort:
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ldmia sp!, {r2 - r3} @ pop virt SP, phys resume fn
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ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
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teq r0, #0
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moveq r0, #1 @ force non-zero value
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mov sp, r2
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@ -69,9 +71,6 @@ ENDPROC(cpu_suspend_abort)
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/*
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* r0 = control register value
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* r1 = v:p offset (preserved by cpu_do_resume)
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* r2 = phys page table base
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* r3 = L1 section flags
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*/
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ENTRY(cpu_resume_mmu)
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ldr r3, =cpu_resume_after_mmu
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@ -112,11 +111,11 @@ ENTRY(cpu_resume)
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ldr r0, sleep_save_sp @ stack phys addr
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#endif
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
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@ load stack, resume fn
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ARM( ldmia r0!, {sp, pc} )
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THUMB( ldmia r0!, {r2, r3} )
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THUMB( mov sp, r2 )
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THUMB( bx r3 )
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@ load phys pgd, stack, resume fn
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ARM( ldmia r0!, {r1, sp, pc} )
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THUMB( ldmia r0!, {r1, r2, r3} )
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THUMB( mov sp, r2 )
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THUMB( bx r3 )
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ENDPROC(cpu_resume)
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sleep_save_sp:
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@ -24,14 +24,17 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
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return -EINVAL;
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/*
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* Temporarily switch the page tables to our suspend page
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* tables, which contain the temporary identity mapping
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* required for resuming.
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* Provide a temporary page table with an identity mapping for
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* the MMU-enable code, required for resuming. On successful
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* resume (indicated by a zero return code), we need to switch
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* back to the correct page tables.
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*/
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cpu_switch_mm(suspend_pgd, mm);
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ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
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cpu_switch_mm(mm->pgd, mm);
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local_flush_tlb_all();
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ret = __cpu_suspend(virt_to_phys(suspend_pgd),
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PHYS_OFFSET - PAGE_OFFSET, arg, fn);
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if (ret == 0) {
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cpu_switch_mm(mm->pgd, mm);
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local_flush_tlb_all();
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}
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return ret;
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}
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@ -379,27 +379,26 @@ ENTRY(cpu_arm920_set_pte_ext)
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/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
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.globl cpu_arm920_suspend_size
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.equ cpu_arm920_suspend_size, 4 * 4
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.equ cpu_arm920_suspend_size, 4 * 3
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_arm920_do_suspend)
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stmfd sp!, {r4 - r7, lr}
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stmfd sp!, {r4 - r6, lr}
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mrc p15, 0, r4, c13, c0, 0 @ PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ TTB address
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mrc p15, 0, r7, c1, c0, 0 @ Control register
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stmia r0, {r4 - r7}
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ldmfd sp!, {r4 - r7, pc}
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mrc p15, 0, r6, c1, c0, 0 @ Control register
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stmia r0, {r4 - r6}
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(cpu_arm920_do_suspend)
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ENTRY(cpu_arm920_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
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ldmia r0, {r4 - r7}
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ldmia r0, {r4 - r6}
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mcr p15, 0, r4, c13, c0, 0 @ PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ TTB address
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mov r0, r7 @ control register
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mcr p15, 0, r1, c2, c0, 0 @ TTB address
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mov r0, r6 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_arm920_do_resume)
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#endif
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@ -394,27 +394,26 @@ ENTRY(cpu_arm926_set_pte_ext)
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/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
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.globl cpu_arm926_suspend_size
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.equ cpu_arm926_suspend_size, 4 * 4
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.equ cpu_arm926_suspend_size, 4 * 3
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_arm926_do_suspend)
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stmfd sp!, {r4 - r7, lr}
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stmfd sp!, {r4 - r6, lr}
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mrc p15, 0, r4, c13, c0, 0 @ PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ TTB address
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mrc p15, 0, r7, c1, c0, 0 @ Control register
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stmia r0, {r4 - r7}
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ldmfd sp!, {r4 - r7, pc}
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mrc p15, 0, r6, c1, c0, 0 @ Control register
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stmia r0, {r4 - r6}
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(cpu_arm926_do_suspend)
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ENTRY(cpu_arm926_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
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ldmia r0, {r4 - r7}
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ldmia r0, {r4 - r6}
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mcr p15, 0, r4, c13, c0, 0 @ PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ TTB address
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mov r0, r7 @ control register
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mcr p15, 0, r1, c2, c0, 0 @ TTB address
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mov r0, r6 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_arm926_do_resume)
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#endif
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@ -168,20 +168,19 @@ ENTRY(cpu_sa1100_set_pte_ext)
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mov pc, lr
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.globl cpu_sa1100_suspend_size
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.equ cpu_sa1100_suspend_size, 4*4
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.equ cpu_sa1100_suspend_size, 4 * 3
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_sa1100_do_suspend)
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stmfd sp!, {r4 - r7, lr}
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stmfd sp!, {r4 - r6, lr}
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mrc p15, 0, r4, c3, c0, 0 @ domain ID
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mrc p15, 0, r5, c2, c0, 0 @ translation table base addr
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mrc p15, 0, r6, c13, c0, 0 @ PID
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mrc p15, 0, r7, c1, c0, 0 @ control reg
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stmia r0, {r4 - r7} @ store cp regs
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ldmfd sp!, {r4 - r7, pc}
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mrc p15, 0, r5, c13, c0, 0 @ PID
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mrc p15, 0, r6, c1, c0, 0 @ control reg
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stmia r0, {r4 - r6} @ store cp regs
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(cpu_sa1100_do_suspend)
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ENTRY(cpu_sa1100_do_resume)
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ldmia r0, {r4 - r7} @ load cp regs
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ldmia r0, {r4 - r6} @ load cp regs
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
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mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
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@ -189,9 +188,9 @@ ENTRY(cpu_sa1100_do_resume)
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mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
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mcr p15, 0, r4, c3, c0, 0 @ domain ID
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mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r6, c13, c0, 0 @ PID
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mov r0, r7 @ control register
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mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r5, c13, c0, 0 @ PID
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mov r0, r6 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_sa1100_do_resume)
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#endif
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@ -128,20 +128,19 @@ ENTRY(cpu_v6_set_pte_ext)
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/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
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.globl cpu_v6_suspend_size
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.equ cpu_v6_suspend_size, 4 * 8
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.equ cpu_v6_suspend_size, 4 * 7
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_v6_do_suspend)
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stmfd sp!, {r4 - r11, lr}
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stmfd sp!, {r4 - r10, lr}
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c13, c0, 1 @ Context ID
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0
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mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1
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mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register
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mrc p15, 0, r10, c1, c0, 2 @ co-processor access control
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mrc p15, 0, r11, c1, c0, 0 @ control register
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stmia r0, {r4 - r11}
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ldmfd sp!, {r4- r11, pc}
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mrc p15, 0, r7, c2, c0, 1 @ Translation table base 1
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mrc p15, 0, r8, c1, c0, 1 @ auxiliary control register
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mrc p15, 0, r9, c1, c0, 2 @ co-processor access control
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mrc p15, 0, r10, c1, c0, 0 @ control register
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stmia r0, {r4 - r10}
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ldmfd sp!, {r4- r10, pc}
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ENDPROC(cpu_v6_do_suspend)
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ENTRY(cpu_v6_do_resume)
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@ -150,17 +149,19 @@ ENTRY(cpu_v6_do_resume)
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
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ldmia r0, {r4 - r11}
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ldmia r0, {r4 - r10}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 1 @ Context ID
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0
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mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1
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mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register
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mcr p15, 0, r10, c1, c0, 2 @ co-processor access control
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ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
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ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
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mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
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mcr p15, 0, r7, c2, c0, 1 @ Translation table base 1
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mcr p15, 0, r8, c1, c0, 1 @ auxiliary control register
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mcr p15, 0, r9, c1, c0, 2 @ co-processor access control
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mcr p15, 0, ip, c2, c0, 2 @ TTB control register
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mcr p15, 0, ip, c7, c5, 4 @ ISB
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mov r0, r11 @ control register
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mov r0, r10 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_v6_do_resume)
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#endif
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@ -217,22 +217,21 @@ ENDPROC(cpu_v7_set_pte_ext)
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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.equ cpu_v7_suspend_size, 4 * 9
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.equ cpu_v7_suspend_size, 4 * 8
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r11, lr}
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stmfd sp!, {r4 - r10, lr}
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c13, c0, 1 @ Context ID
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mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
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stmia r0!, {r4 - r6}
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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mrc p15, 0, r7, c2, c0, 0 @ TTB 0
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mrc p15, 0, r8, c2, c0, 1 @ TTB 1
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mrc p15, 0, r9, c1, c0, 0 @ Control register
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mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
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stmia r0, {r6 - r11}
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ldmfd sp!, {r4 - r11, pc}
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mrc p15, 0, r7, c2, c0, 1 @ TTB 1
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mrc p15, 0, r8, c1, c0, 0 @ Control register
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mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
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stmia r0, {r6 - r10}
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ldmfd sp!, {r4 - r10, pc}
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ENDPROC(cpu_v7_do_suspend)
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ENTRY(cpu_v7_do_resume)
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@ -243,22 +242,24 @@ ENTRY(cpu_v7_do_resume)
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 1 @ Context ID
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mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
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ldmia r0, {r6 - r11}
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ldmia r0, {r6 - r10}
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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mcr p15, 0, r7, c2, c0, 0 @ TTB 0
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mcr p15, 0, r8, c2, c0, 1 @ TTB 1
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ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
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ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
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mcr p15, 0, r1, c2, c0, 0 @ TTB 0
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mcr p15, 0, r7, c2, c0, 1 @ TTB 1
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mcr p15, 0, ip, c2, c0, 2 @ TTB control register
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mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
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teq r4, r10 @ Is it already set?
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mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
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mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
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teq r4, r9 @ Is it already set?
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mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
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mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
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ldr r4, =PRRR @ PRRR
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ldr r5, =NMRR @ NMRR
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mcr p15, 0, r4, c10, c2, 0 @ write PRRR
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mcr p15, 0, r5, c10, c2, 1 @ write NMRR
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isb
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dsb
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mov r0, r9 @ control register
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mov r0, r8 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_v7_do_resume)
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#endif
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@ -406,24 +406,23 @@ ENTRY(cpu_xsc3_set_pte_ext)
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.align
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.globl cpu_xsc3_suspend_size
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.equ cpu_xsc3_suspend_size, 4 * 7
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.equ cpu_xsc3_suspend_size, 4 * 6
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_xsc3_do_suspend)
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stmfd sp!, {r4 - r10, lr}
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stmfd sp!, {r4 - r9, lr}
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mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
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mrc p15, 0, r5, c15, c1, 0 @ CP access reg
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mrc p15, 0, r6, c13, c0, 0 @ PID
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mrc p15, 0, r7, c3, c0, 0 @ domain ID
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mrc p15, 0, r8, c2, c0, 0 @ translation table base addr
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mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg
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mrc p15, 0, r10, c1, c0, 0 @ control reg
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mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
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mrc p15, 0, r9, c1, c0, 0 @ control reg
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bic r4, r4, #2 @ clear frequency change bit
|
||||
stmia r0, {r4 - r10} @ store cp regs
|
||||
ldmia sp!, {r4 - r10, pc}
|
||||
stmia r0, {r4 - r9} @ store cp regs
|
||||
ldmia sp!, {r4 - r9, pc}
|
||||
ENDPROC(cpu_xsc3_do_suspend)
|
||||
|
||||
ENTRY(cpu_xsc3_do_resume)
|
||||
ldmia r0, {r4 - r10} @ load cp regs
|
||||
ldmia r0, {r4 - r9} @ load cp regs
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
|
||||
|
|
@ -433,9 +432,10 @@ ENTRY(cpu_xsc3_do_resume)
|
|||
mcr p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mcr p15, 0, r6, c13, c0, 0 @ PID
|
||||
mcr p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg
|
||||
mov r0, r10 @ control register
|
||||
orr r1, r1, #0x18 @ cache the page table in L2
|
||||
mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
||||
mov r0, r9 @ control register
|
||||
b cpu_resume_mmu
|
||||
ENDPROC(cpu_xsc3_do_resume)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -520,24 +520,23 @@ ENTRY(cpu_xscale_set_pte_ext)
|
|||
.align
|
||||
|
||||
.globl cpu_xscale_suspend_size
|
||||
.equ cpu_xscale_suspend_size, 4 * 7
|
||||
.equ cpu_xscale_suspend_size, 4 * 6
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
ENTRY(cpu_xscale_do_suspend)
|
||||
stmfd sp!, {r4 - r10, lr}
|
||||
stmfd sp!, {r4 - r9, lr}
|
||||
mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
|
||||
mrc p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mrc p15, 0, r6, c13, c0, 0 @ PID
|
||||
mrc p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mrc p15, 0, r8, c2, c0, 0 @ translation table base addr
|
||||
mrc p15, 0, r9, c1, c1, 0 @ auxiliary control reg
|
||||
mrc p15, 0, r10, c1, c0, 0 @ control reg
|
||||
mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
|
||||
mrc p15, 0, r9, c1, c0, 0 @ control reg
|
||||
bic r4, r4, #2 @ clear frequency change bit
|
||||
stmia r0, {r4 - r10} @ store cp regs
|
||||
ldmfd sp!, {r4 - r10, pc}
|
||||
stmia r0, {r4 - r9} @ store cp regs
|
||||
ldmfd sp!, {r4 - r9, pc}
|
||||
ENDPROC(cpu_xscale_do_suspend)
|
||||
|
||||
ENTRY(cpu_xscale_do_resume)
|
||||
ldmia r0, {r4 - r10} @ load cp regs
|
||||
ldmia r0, {r4 - r9} @ load cp regs
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
|
||||
|
|
@ -545,9 +544,9 @@ ENTRY(cpu_xscale_do_resume)
|
|||
mcr p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mcr p15, 0, r6, c13, c0, 0 @ PID
|
||||
mcr p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg
|
||||
mov r0, r10 @ control register
|
||||
mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
|
||||
mov r0, r9 @ control register
|
||||
b cpu_resume_mmu
|
||||
ENDPROC(cpu_xscale_do_resume)
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue