Reset controller changes for v4.18
This adds PCIe, SATA, and HSC reset control support on various Uniphier SoCs. PCIe reset control is added for Pro5, LD20, and PXs3 SoCs, SATA reset control support is added on Pro4 and PXs3 SoCs. The previously added PXs2 SATA reset control identifier is changed to the same value for consistency. HSC (MPEG2 transport stream I/O and demux system) reset controls are added for LD11 and LD20 SoCs. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCWvmu/hcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwKEqAP9K8vtILr1MDJjyK5TXL+gpnv5b VC8214bEI5inlNDKmQEAplh+qfSI97QGBg06uV7kp2agOvc2yKd9EMUqcnq1WgM= =rMPh -----END PGP SIGNATURE----- Merge tag 'reset-for-4.18' of git://git.pengutronix.de/pza/linux into next/drivers Reset controller changes for v4.18 This adds PCIe, SATA, and HSC reset control support on various Uniphier SoCs. PCIe reset control is added for Pro5, LD20, and PXs3 SoCs, SATA reset control support is added on Pro4 and PXs3 SoCs. The previously added PXs2 SATA reset control identifier is changed to the same value for consistency. HSC (MPEG2 transport stream I/O and demux system) reset controls are added for LD11 and LD20 SoCs. * tag 'reset-for-4.18' of git://git.pengutronix.de/pza/linux: reset: uniphier: add LD11/LD20 stream demux system reset control reset: uniphier: add SATA reset control support and change SATA-PHY ID reset: uniphier: add PCIe reset control support reset: uniphier: fix USB clock line for LD20 Signed-off-by: Olof Johansson <olof@lixom.net>
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@ -63,6 +63,9 @@ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
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UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
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UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
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UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
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UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
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UNIPHIER_RESETX(29, 0x2004, 18), /* SATA1 */
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UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */
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UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
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UNIPHIER_RESET_END,
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};
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@ -73,6 +76,7 @@ static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
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UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */
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UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
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UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
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UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */
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UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
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UNIPHIER_RESET_END,
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};
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@ -89,7 +93,7 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
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UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
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UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
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UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
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UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
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UNIPHIER_RESET(30, 0x2014, 8), /* SATA-PHY (active high) */
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UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
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UNIPHIER_RESET_END,
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};
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@ -99,6 +103,7 @@ static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
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UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
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UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
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UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC, MIO) */
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UNIPHIER_RESETX(9, 0x200c, 9), /* HSC */
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UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
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UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */
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UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */
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@ -110,11 +115,13 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
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UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
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UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
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UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */
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UNIPHIER_RESETX(12, 0x200c, 5), /* GIO (PCIe, USB3) */
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UNIPHIER_RESETX(9, 0x200c, 9), /* HSC */
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UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */
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UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
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UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
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UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
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UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
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UNIPHIER_RESETX(24, 0x200c, 4), /* PCIe */
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UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
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UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */
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UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */
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@ -127,13 +134,17 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
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UNIPHIER_RESETX(6, 0x200c, 9), /* Ether0 */
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UNIPHIER_RESETX(7, 0x200c, 10), /* Ether1 */
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UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
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UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link (GIO0) */
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UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link (GIO1) */
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UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */
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UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */
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UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
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UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
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UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
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UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */
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UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */
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UNIPHIER_RESETX(24, 0x200c, 3), /* PCIe */
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UNIPHIER_RESETX(28, 0x200c, 7), /* SATA0 */
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UNIPHIER_RESETX(29, 0x200c, 8), /* SATA1 */
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UNIPHIER_RESETX(30, 0x200c, 21), /* SATA-PHY */
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UNIPHIER_RESET_END,
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};
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