drm/i915: Simplify ironlake_crtc_compute_clock() CPU eDP case
None of the code in ironlake_crtc_compute_clock() is relevant for CPU eDP. The CPU eDP PLL is turned on and off in ironlake_edp_pll_{on,off} from the DP code and that doesn't depend on the crtc_state->dpll values, so just return early in that case. v2: Rebase without patch that drops lvds downclock code. (Ville) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-9-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -8800,13 +8800,16 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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intel_clock_t clock, reduced_clock;
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u32 dpll = 0, fp = 0, fp2 = 0;
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bool has_reduced_clock = false;
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bool is_lvds = false;
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struct intel_shared_dpll *pll;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
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crtc->lowfreq_avail = false;
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/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
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if (!crtc_state->has_pch_encoder)
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return 0;
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if (!crtc_state->clock_set) {
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if (!ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
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@ -8824,34 +8827,30 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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crtc_state->dpll.p2 = clock.p2;
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}
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/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
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if (crtc_state->has_pch_encoder) {
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fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
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if (has_reduced_clock)
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fp2 = i9xx_dpll_compute_fp(&reduced_clock);
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else
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fp2 = fp;
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fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
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if (has_reduced_clock)
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fp2 = i9xx_dpll_compute_fp(&reduced_clock);
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else
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fp2 = fp;
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dpll = ironlake_compute_dpll(crtc, crtc_state,
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&fp, &reduced_clock,
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has_reduced_clock ? &fp2 : NULL);
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dpll = ironlake_compute_dpll(crtc, crtc_state,
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&fp, &reduced_clock,
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has_reduced_clock ? &fp2 : NULL);
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crtc_state->dpll_hw_state.dpll = dpll;
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crtc_state->dpll_hw_state.fp0 = fp;
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crtc_state->dpll_hw_state.fp1 = fp2;
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crtc_state->dpll_hw_state.dpll = dpll;
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crtc_state->dpll_hw_state.fp0 = fp;
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crtc_state->dpll_hw_state.fp1 = fp2;
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pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
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if (pll == NULL) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
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pipe_name(crtc->pipe));
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return -EINVAL;
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}
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pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
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if (pll == NULL) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
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pipe_name(crtc->pipe));
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return -EINVAL;
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}
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if (is_lvds && has_reduced_clock)
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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has_reduced_clock)
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crtc->lowfreq_avail = true;
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else
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crtc->lowfreq_avail = false;
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return 0;
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}
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