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staging: iio: ad2s1210: Fix SPI reading 

commit 5e4f99a6b7 upstream.

If the serial interface is used, the 8-bit address should be latched using
the rising edge of the WR/FSYNC signal.

This basically means that a CS change is required between the first byte
sent, and the second one.
This change splits the single-transfer transfer of 2 bytes into 2 transfers
with a single byte, and CS change in-between.

Note fixes tag is not accurate, but reflects a point beyond which there
are too many refactors to make backporting straight forward.

Fixes: b19e9ad5e2 ("staging:iio:resolver:ad2s1210 general driver cleanup.")
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5.4-rM2-2.2.x-imx-squashed
Dragos Bogdan 2020-04-29 10:21:29 +03:00 committed by Greg Kroah-Hartman
parent 76296dc723
commit dee81110a4
1 changed files with 12 additions and 5 deletions
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17
drivers/staging/iio/resolver/ad2s1210.c
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@ -130,17 +130,24 @@ static int ad2s1210_config_write(struct ad2s1210_state *st, u8 data)
static int ad2s1210_config_read(struct ad2s1210_state *st,
unsigned char address)
{
struct spi_transfer xfer = {
.len = 2,
.rx_buf = st->rx,
.tx_buf = st->tx,
struct spi_transfer xfers[] = {
{
.len = 1,
.rx_buf = &st->rx[0],
.tx_buf = &st->tx[0],
.cs_change = 1,
}, {
.len = 1,
.rx_buf = &st->rx[1],
.tx_buf = &st->tx[1],
},
};
int ret = 0;
ad2s1210_set_mode(MOD_CONFIG, st);
st->tx[0] = address | AD2S1210_MSB_IS_HIGH;
st->tx[1] = AD2S1210_REG_FAULT;
ret = spi_sync_transfer(st->sdev, &xfer, 1);
ret = spi_sync_transfer(st->sdev, xfers, 2);
if (ret < 0)
return ret;