dts: vt8500: Add initial dts support for WM8850
This patch adds a soc dtsi for the Wondermedia WM8850. A board dts file is also included for the W70v2 tablet, with support for all the drivers currently in mainline. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Olof Johansson <olof@lixom.net>hifive-unleashed-5.1
Tony Prisk
Olof Johansson
parent
8d31bfa551
commit
def4d6c044
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@ -151,7 +151,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
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xenvm-4.2.dtb
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dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
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wm8505-ref.dtb \
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wm8650-mid.dtb
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wm8650-mid.dtb \
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wm8850-w70v2.dtb
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dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
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targets += dtbs
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@ -0,0 +1,47 @@
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/*
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* wm8850-w70v2.dts
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* - Device tree file for Wondermedia WM8850 Tablet
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* - 'W70-V2' mainboard
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* - HongLianYing 'HLY070ML268-21A' 7" LCD panel
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*
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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*
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* Licensed under GPLv2 or later
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*/
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/dts-v1/;
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/include/ "wm8850.dtsi"
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/ {
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model = "Wondermedia WM8850-W70v2 Tablet";
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/*
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* Display node is based on Sascha Hauer's patch on dri-devel.
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* Added a bpp property to calculate the size of the framebuffer
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* until the binding is formalized.
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*/
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display: display@0 {
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modes {
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mode0: mode@0 {
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hactive = <800>;
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vactive = <480>;
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hback-porch = <88>;
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hfront-porch = <40>;
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hsync-len = <0>;
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vback-porch = <32>;
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vfront-porch = <11>;
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vsync-len = <1>;
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clock = <0>; /* unused but required */
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bpp = <16>; /* non-standard but required */
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};
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};
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm 0 50000 1>; /* duty inverted */
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brightness-levels = <0 40 60 80 100 130 190 255>;
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default-brightness-level = <5>;
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};
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};
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@ -0,0 +1,224 @@
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/*
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* wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
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*
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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*
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* Licensed under GPLv2 or later
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "wm,wm8850";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&intc0>;
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intc0: interrupt-controller@d8140000 {
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compatible = "via,vt8500-intc";
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interrupt-controller;
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reg = <0xd8140000 0x10000>;
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#interrupt-cells = <1>;
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};
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/* Secondary IC cascaded to intc0 */
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intc1: interrupt-controller@d8150000 {
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compatible = "via,vt8500-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xD8150000 0x10000>;
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interrupts = <56 57 58 59 60 61 62 63>;
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};
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gpio: gpio-controller@d8110000 {
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compatible = "wm,wm8650-gpio";
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gpio-controller;
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reg = <0xd8110000 0x10000>;
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#gpio-cells = <3>;
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};
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pmc@d8130000 {
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compatible = "via,vt8500-pmc";
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reg = <0xd8130000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ref25: ref25M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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ref24: ref24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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plla: plla {
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#clock-cells = <0>;
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compatible = "wm,wm8750-pll-clock";
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clocks = <&ref25>;
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reg = <0x200>;
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};
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pllb: pllb {
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#clock-cells = <0>;
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compatible = "wm,wm8750-pll-clock";
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clocks = <&ref25>;
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reg = <0x204>;
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};
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clkuart0: uart0 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <24>;
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};
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clkuart1: uart1 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <25>;
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};
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clkuart2: uart2 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <26>;
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};
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clkuart3: uart3 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x254>;
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enable-bit = <27>;
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};
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clkpwm: pwm {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x350>;
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enable-reg = <0x250>;
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enable-bit = <17>;
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};
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clksdhc: sdhc {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x330>;
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divisor-mask = <0x3f>;
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enable-reg = <0x250>;
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enable-bit = <0>;
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};
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};
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};
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fb@d8051700 {
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compatible = "wm,wm8505-fb";
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reg = <0xd8051700 0x200>;
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display = <&display>;
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default-mode = <&mode0>;
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};
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ge_rops@d8050400 {
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compatible = "wm,prizm-ge-rops";
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reg = <0xd8050400 0x100>;
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};
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pwm: pwm@d8220000 {
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#pwm-cells = <3>;
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compatible = "via,vt8500-pwm";
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reg = <0xd8220000 0x100>;
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clocks = <&clkpwm>;
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};
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timer@d8130100 {
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compatible = "via,vt8500-timer";
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reg = <0xd8130100 0x28>;
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interrupts = <36>;
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};
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ehci@d8007900 {
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compatible = "via,vt8500-ehci";
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reg = <0xd8007900 0x200>;
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interrupts = <26>;
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};
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uhci@d8007b00 {
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compatible = "platform-uhci";
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reg = <0xd8007b00 0x200>;
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interrupts = <26>;
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};
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uhci@d8008d00 {
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compatible = "platform-uhci";
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reg = <0xd8008d00 0x200>;
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interrupts = <26>;
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};
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uart0: uart@d8200000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8200000 0x1040>;
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interrupts = <32>;
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clocks = <&clkuart0>;
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};
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uart1: uart@d82b0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82b0000 0x1040>;
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interrupts = <33>;
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clocks = <&clkuart1>;
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};
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uart2: uart@d8210000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8210000 0x1040>;
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interrupts = <47>;
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clocks = <&clkuart2>;
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};
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uart3: uart@d82c0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82c0000 0x1040>;
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interrupts = <50>;
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clocks = <&clkuart3>;
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};
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rtc@d8100000 {
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compatible = "via,vt8500-rtc";
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reg = <0xd8100000 0x10000>;
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interrupts = <48>;
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};
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sdhc@d800a000 {
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compatible = "wm,wm8505-sdhc";
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reg = <0xd800a000 0x1000>;
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interrupts = <20 21>;
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clocks = <&clksdhc>;
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bus-width = <4>;
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sdon-inverted;
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};
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};
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};
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