clk: bcm: rpi: Use CCF boundaries instead of rolling our own
The raspberrypi firmware clock driver has a min_rate / max_rate clamping by storing the info it needs in a private structure. However, the CCF already provides such a facility, so we can switch to it to remove the boilerplate. Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/d4c53dab6de5d5f70743d9c139d0117589530e62.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -36,9 +36,6 @@ struct raspberrypi_clk {
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struct rpi_firmware *firmware;
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struct platform_device *cpufreq;
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unsigned long min_rate;
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unsigned long max_rate;
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struct clk_hw pllb;
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};
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@ -142,13 +139,11 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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pllb);
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u64 div, final_rate;
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u32 ndiv, fdiv;
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/* We can't use req->rate directly as it would overflow */
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final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
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final_rate = clamp(req->rate, req->min_rate, req->max_rate);
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div = (u64)final_rate << A2W_PLL_FRAC_BITS;
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do_div(div, req->best_parent_rate);
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@ -215,12 +210,15 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
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dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
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min_rate, max_rate);
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rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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rpi->pllb.init = &init;
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return devm_clk_hw_register(rpi->dev, &rpi->pllb);
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ret = devm_clk_hw_register(rpi->dev, &rpi->pllb);
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if (!ret)
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clk_hw_set_rate_range(&rpi->pllb,
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min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE,
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max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE);
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return ret;
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}
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static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
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