powerpc/pseries: Update ibm,architecture.vec for PAPR 2.7/POWER8
Update ibm,architecture.vec for POWER8 and allows us to support more than one parition per core. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -671,6 +671,7 @@ static void __init early_cmdline_parse(void)
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#define OV1_PPC_2_04 0x08 /* set if we support PowerPC 2.04 */
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#define OV1_PPC_2_04 0x08 /* set if we support PowerPC 2.04 */
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#define OV1_PPC_2_05 0x04 /* set if we support PowerPC 2.05 */
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#define OV1_PPC_2_05 0x04 /* set if we support PowerPC 2.05 */
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#define OV1_PPC_2_06 0x02 /* set if we support PowerPC 2.06 */
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#define OV1_PPC_2_06 0x02 /* set if we support PowerPC 2.06 */
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#define OV1_PPC_2_07 0x01 /* set if we support PowerPC 2.07 */
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/* Option vector 2: Open Firmware options supported */
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/* Option vector 2: Open Firmware options supported */
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#define OV2_REAL_MODE 0x20 /* set if we want OF in real mode */
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#define OV2_REAL_MODE 0x20 /* set if we want OF in real mode */
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@ -707,6 +708,7 @@ static void __init early_cmdline_parse(void)
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#define OV5_PFO_HW_RNG 0x80 /* PFO Random Number Generator */
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#define OV5_PFO_HW_RNG 0x80 /* PFO Random Number Generator */
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#define OV5_PFO_HW_842 0x40 /* PFO Compression Accelerator */
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#define OV5_PFO_HW_842 0x40 /* PFO Compression Accelerator */
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#define OV5_PFO_HW_ENCR 0x20 /* PFO Encryption Accelerator */
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#define OV5_PFO_HW_ENCR 0x20 /* PFO Encryption Accelerator */
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#define OV5_SUB_PROCESSORS 0x01 /* 1,2,or 4 Sub-Processors supported */
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/* Option Vector 6: IBM PAPR hints */
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/* Option Vector 6: IBM PAPR hints */
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#define OV6_LINUX 0x02 /* Linux is our OS */
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#define OV6_LINUX 0x02 /* Linux is our OS */
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@ -719,6 +721,8 @@ static unsigned char ibm_architecture_vec[] = {
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W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */
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W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */
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W(0xffff0000), W(0x003e0000), /* POWER6 */
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W(0xffff0000), W(0x003e0000), /* POWER6 */
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W(0xffff0000), W(0x003f0000), /* POWER7 */
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W(0xffff0000), W(0x003f0000), /* POWER7 */
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W(0xffff0000), W(0x004b0000), /* POWER8 */
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W(0xffffffff), W(0x0f000004), /* all 2.07-compliant */
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W(0xffffffff), W(0x0f000003), /* all 2.06-compliant */
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W(0xffffffff), W(0x0f000003), /* all 2.06-compliant */
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W(0xffffffff), W(0x0f000002), /* all 2.05-compliant */
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W(0xffffffff), W(0x0f000002), /* all 2.05-compliant */
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W(0xfffffffe), W(0x0f000001), /* all 2.04-compliant and earlier */
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W(0xfffffffe), W(0x0f000001), /* all 2.04-compliant and earlier */
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@ -728,7 +732,7 @@ static unsigned char ibm_architecture_vec[] = {
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3 - 2, /* length */
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3 - 2, /* length */
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0, /* don't ignore, don't halt */
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0, /* don't ignore, don't halt */
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OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
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OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
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OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06,
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OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07,
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/* option vector 2: Open Firmware options supported */
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/* option vector 2: Open Firmware options supported */
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34 - 2, /* length */
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34 - 2, /* length */
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@ -755,7 +759,7 @@ static unsigned char ibm_architecture_vec[] = {
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OV4_MIN_ENT_CAP, /* minimum VP entitled capacity */
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OV4_MIN_ENT_CAP, /* minimum VP entitled capacity */
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/* option vector 5: PAPR/OF options */
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/* option vector 5: PAPR/OF options */
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18 - 2, /* length */
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19 - 2, /* length */
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0, /* don't ignore, don't halt */
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0, /* don't ignore, don't halt */
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OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES | OV5_DRCONF_MEMORY |
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OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES | OV5_DRCONF_MEMORY |
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OV5_DONATE_DEDICATE_CPU | OV5_MSI,
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OV5_DONATE_DEDICATE_CPU | OV5_MSI,
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@ -769,13 +773,14 @@ static unsigned char ibm_architecture_vec[] = {
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* must match by the macro below. Update the definition if
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* must match by the macro below. Update the definition if
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* the structure layout changes.
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* the structure layout changes.
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*/
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*/
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#define IBM_ARCH_VEC_NRCORES_OFFSET 101
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#define IBM_ARCH_VEC_NRCORES_OFFSET 117
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W(NR_CPUS), /* number of cores supported */
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W(NR_CPUS), /* number of cores supported */
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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OV5_PFO_HW_RNG | OV5_PFO_HW_ENCR | OV5_PFO_HW_842,
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OV5_PFO_HW_RNG | OV5_PFO_HW_ENCR | OV5_PFO_HW_842,
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OV5_SUB_PROCESSORS,
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/* option vector 6: IBM PAPR hints */
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/* option vector 6: IBM PAPR hints */
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4 - 2, /* length */
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4 - 2, /* length */
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0,
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0,
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