clk: samsung: Add set_rate() clk_ops for PLL35xx
This patch add set_rate() and round_rate() for PLL35xx Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -24,16 +24,51 @@ struct samsung_clk_pll {
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#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
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#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
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static const struct samsung_pll_rate_table *samsung_get_pll_settings(
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struct samsung_clk_pll *pll, unsigned long rate)
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{
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const struct samsung_pll_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++) {
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if (rate == rate_table[i].rate)
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return &rate_table[i];
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}
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return NULL;
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}
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static long samsung_pll_round_rate(struct clk_hw *hw,
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unsigned long drate, unsigned long *prate)
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{
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struct samsung_clk_pll *pll = to_clk_pll(hw);
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const struct samsung_pll_rate_table *rate_table = pll->rate_table;
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int i;
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/* Assumming rate_table is in descending order */
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for (i = 0; i < pll->rate_count; i++) {
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if (drate >= rate_table[i].rate)
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return rate_table[i].rate;
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}
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/* return minimum supported value */
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return rate_table[i - 1].rate;
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}
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/*
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/*
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* PLL35xx Clock Type
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* PLL35xx Clock Type
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*/
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*/
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/* Maximum lock time can be 270 * PDIV cycles */
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#define PLL35XX_LOCK_FACTOR (270)
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#define PLL35XX_MDIV_MASK (0x3FF)
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#define PLL35XX_MDIV_MASK (0x3FF)
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#define PLL35XX_PDIV_MASK (0x3F)
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#define PLL35XX_PDIV_MASK (0x3F)
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#define PLL35XX_SDIV_MASK (0x7)
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#define PLL35XX_SDIV_MASK (0x7)
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#define PLL35XX_LOCK_STAT_MASK (0x1)
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#define PLL35XX_MDIV_SHIFT (16)
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#define PLL35XX_MDIV_SHIFT (16)
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#define PLL35XX_PDIV_SHIFT (8)
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#define PLL35XX_PDIV_SHIFT (8)
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#define PLL35XX_SDIV_SHIFT (0)
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#define PLL35XX_SDIV_SHIFT (0)
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#define PLL35XX_LOCK_STAT_SHIFT (29)
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static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
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static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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unsigned long parent_rate)
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@ -53,8 +88,73 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
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return (unsigned long)fvco;
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return (unsigned long)fvco;
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}
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}
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static inline bool samsung_pll35xx_mp_change(
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const struct samsung_pll_rate_table *rate, u32 pll_con)
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{
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u32 old_mdiv, old_pdiv;
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old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
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old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
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return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
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}
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static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct samsung_clk_pll *pll = to_clk_pll(hw);
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const struct samsung_pll_rate_table *rate;
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u32 tmp;
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/* Get required rate settings from table */
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rate = samsung_get_pll_settings(pll, drate);
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if (!rate) {
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pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
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drate, __clk_get_name(hw->clk));
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return -EINVAL;
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}
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tmp = __raw_readl(pll->con_reg);
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if (!(samsung_pll35xx_mp_change(rate, tmp))) {
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/* If only s change, change just s value only*/
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tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
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tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
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__raw_writel(tmp, pll->con_reg);
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return 0;
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}
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/* Set PLL lock time. */
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__raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR,
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pll->lock_reg);
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/* Change PLL PMS values */
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tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
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(PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
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(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
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tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
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(rate->pdiv << PLL35XX_PDIV_SHIFT) |
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(rate->sdiv << PLL35XX_SDIV_SHIFT);
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__raw_writel(tmp, pll->con_reg);
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/* wait_lock_time */
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do {
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cpu_relax();
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tmp = __raw_readl(pll->con_reg);
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} while (!(tmp & (PLL35XX_LOCK_STAT_MASK
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<< PLL35XX_LOCK_STAT_SHIFT)));
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return 0;
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}
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static const struct clk_ops samsung_pll35xx_clk_ops = {
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static const struct clk_ops samsung_pll35xx_clk_ops = {
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.recalc_rate = samsung_pll35xx_recalc_rate,
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.recalc_rate = samsung_pll35xx_recalc_rate,
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.round_rate = samsung_pll_round_rate,
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.set_rate = samsung_pll35xx_set_rate,
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};
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static const struct clk_ops samsung_pll35xx_clk_min_ops = {
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.recalc_rate = samsung_pll35xx_recalc_rate,
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};
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};
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/*
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/*
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@ -385,7 +485,10 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
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/* clk_ops for 35xx and 2550 are similar */
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/* clk_ops for 35xx and 2550 are similar */
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case pll_35xx:
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case pll_35xx:
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case pll_2550:
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case pll_2550:
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init.ops = &samsung_pll35xx_clk_ops;
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if (!pll->rate_table)
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init.ops = &samsung_pll35xx_clk_min_ops;
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else
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init.ops = &samsung_pll35xx_clk_ops;
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break;
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break;
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/* clk_ops for 36xx and 2650 are similar */
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/* clk_ops for 36xx and 2650 are similar */
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case pll_36xx:
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case pll_36xx:
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