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drm/i915: correctly set the DDI_FUNC_CTL bpc field 

Correctly erase the values previously set and also check for 6bpc and
10bpc.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
hifive-unleashed-5.1
Paulo Zanoni 2012-08-08 14:15:29 -03:00 committed by Daniel Vetter
parent f63eb7c452
commit dfcef252e0
2 changed files with 21 additions and 6 deletions
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1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -4308,6 +4308,7 @@
#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
#define PIPE_DDI_MODE_SELECT_FDI (4<<24)
#define PIPE_DDI_BPC_MASK (7<<20)
#define PIPE_DDI_BPC_8 (0<<20)
#define PIPE_DDI_BPC_10 (1<<20)
#define PIPE_DDI_BPC_6 (2<<20)

26
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -725,14 +725,28 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = I915_READ(DDI_FUNC_CTL(pipe));
temp &= ~PIPE_DDI_PORT_MASK;
temp &= ~PIPE_DDI_BPC_12;
temp &= ~PIPE_DDI_BPC_MASK;
temp &= ~PIPE_DDI_MODE_SELECT_MASK;
temp &= ~(PIPE_DDI_PVSYNC | PIPE_DDI_PHSYNC);
temp |= PIPE_DDI_SELECT_PORT(port) |
((intel_crtc->bpp > 24) ?
PIPE_DDI_BPC_12 :
PIPE_DDI_BPC_8) |
PIPE_DDI_FUNC_ENABLE;
temp |= PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port);
switch (intel_crtc->bpp) {
case 18:
temp |= PIPE_DDI_BPC_6;
break;
case 24:
temp |= PIPE_DDI_BPC_8;
break;
case 30:
temp |= PIPE_DDI_BPC_10;
break;
case 36:
temp |= PIPE_DDI_BPC_12;
break;
default:
WARN(1, "%d bpp unsupported by pipe DDI function\n",
intel_crtc->bpp);
}
if (intel_hdmi->has_hdmi_sink)
temp |= PIPE_DDI_MODE_SELECT_HDMI;