redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

Merge remote-tracking branch 'agust/next' into next 

<<
Please pull mpc5xxx patches for v3.9. The bestcomm driver is
moved to drivers/dma (so it will be usable for ColdFire).
mpc5121 now provides common dtsi file and existing mpc5121 device
trees use it. There are some minor clock init and sparse fixes
and updates for various 5200 device tree files from Grant. Some
fixes for bugs in the mpc5121 DIU driver are also included here
(Andrew Morton suggested to push them via my mpc5xxx tree).
>>
hifive-unleashed-5.1
Benjamin Herrenschmidt 2013-02-20 11:39:05 +11:00
parent 877d66856e fa59f17855
commit dffff02a6b
48 changed files with 719 additions and 847 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/powerpc/boot/dts/a3m071.dts
View File

@ -17,6 +17,8 @@
/include/ "mpc5200b.dtsi"
&gpt0 { fsl,has-wdt; };
/ {
model = "anonymous,a3m071";
compatible = "anonymous,a3m071";
@ -30,10 +32,6 @@
bus-frequency = <0>; /* From boot loader */
system-frequency = <0>; /* From boot loader */
timer@600 {
fsl,has-wdt;
};
spi@f00 {
status = "disabled";
};

27
arch/powerpc/boot/dts/a4m072.dts
View File

@ -15,6 +15,11 @@
/include/ "mpc5200b.dtsi"
&gpt0 { fsl,has-wdt; };
&gpt3 { gpio-controller; };
&gpt4 { gpio-controller; };
&gpt5 { gpio-controller; };
/ {
model = "anonymous,a4m072";
compatible = "anonymous,a4m072";
@ -34,28 +39,6 @@
fsl,init-fd-counters = <0x3333>;
};
timer@600 {
fsl,has-wdt;
};
gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
status = "disabled";
};

6
arch/powerpc/boot/dts/cm5200.dts
View File

@ -12,15 +12,13 @@
/include/ "mpc5200b.dtsi"
&gpt0 { fsl,has-wdt; };
/ {
model = "schindler,cm5200";
compatible = "schindler,cm5200";
soc5200@f0000000 {
timer@600 { // General Purpose Timer
fsl,has-wdt;
};
can@900 {
status = "disabled";
};

14
arch/powerpc/boot/dts/digsy_mtc.dts
View File

@ -13,6 +13,9 @@
/include/ "mpc5200b.dtsi"
&gpt0 { gpio-controller; fsl,has-wdt; };
&gpt1 { gpio-controller; };
/ {
model = "intercontrol,digsy-mtc";
compatible = "intercontrol,digsy-mtc";
@ -22,17 +25,6 @@
};
soc5200@f0000000 {
timer@600 { // General Purpose Timer
#gpio-cells = <2>;
fsl,has-wdt;
gpio-controller;
};
timer@610 {
#gpio-cells = <2>;
gpio-controller;
};
rtc@800 {
status = "disabled";
};

23
arch/powerpc/boot/dts/lite5200b.dts
View File

@ -12,19 +12,34 @@
/include/ "mpc5200b.dtsi"
&gpt0 { fsl,has-wdt; };
&gpt2 { gpio-controller; };
&gpt3 { gpio-controller; };
/ {
model = "fsl,lite5200b";
compatible = "fsl,lite5200b";
leds {
compatible = "gpio-leds";
tmr2 {
gpios = <&gpt2 0 1>;
};
tmr3 {
gpios = <&gpt3 0 1>;
linux,default-trigger = "heartbeat";
};
led1 { gpios = <&gpio_wkup 2 1>; };
led2 { gpios = <&gpio_simple 3 1>; };
led3 { gpios = <&gpio_wkup 3 1>; };
led4 { gpios = <&gpio_simple 2 1>; };
};
memory {
reg = <0x00000000 0x10000000>; // 256MB
};
soc5200@f0000000 {
timer@600 { // General Purpose Timer
fsl,has-wdt;
};
psc@2000 { // PSC1
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
cell-index = <0>;

6
arch/powerpc/boot/dts/media5200.dts
View File

@ -13,6 +13,8 @@
/include/ "mpc5200b.dtsi"
&gpt0 { fsl,has-wdt; };
/ {
model = "fsl,media5200";
compatible = "fsl,media5200";
@ -41,10 +43,6 @@
soc5200@f0000000 {
bus-frequency = <132000000>;// 132 MHz
timer@600 { // General Purpose Timer
fsl,has-wdt;
};
psc@2000 { // PSC1
status = "disabled";
};

26
arch/powerpc/boot/dts/motionpro.dts
View File

@ -12,26 +12,22 @@
/include/ "mpc5200b.dtsi"
&gpt0 { fsl,has-wdt; };
&gpt6 { // Motion-PRO status LED
compatible = "promess,motionpro-led";
label = "motionpro-statusled";
blink-delay = <100>; // 100 msec
};
&gpt7 { // Motion-PRO ready LED
compatible = "promess,motionpro-led";
label = "motionpro-readyled";
};
/ {
model = "promess,motionpro";
compatible = "promess,motionpro";
soc5200@f0000000 {
timer@600 { // General Purpose Timer
fsl,has-wdt;
};
timer@660 { // Motion-PRO status LED
compatible = "promess,motionpro-led";
label = "motionpro-statusled";
blink-delay = <100>; // 100 msec
};
timer@670 { // Motion-PRO ready LED
compatible = "promess,motionpro-led";
label = "motionpro-readyled";
};
can@900 {
status = "disabled";
};

410
arch/powerpc/boot/dts/mpc5121.dtsi 100644
View File

@ -0,0 +1,410 @@
/*
* base MPC5121 Device Tree Source
*
* Copyright 2007-2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "mpc5121";
compatible = "fsl,mpc5121";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&ipic>;
aliases {
ethernet0 = &eth0;
pci = &pci;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5121@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <0x20>; /* 32 bytes */
i-cache-line-size = <0x20>; /* 32 bytes */
d-cache-size = <0x8000>; /* L1, 32K */
i-cache-size = <0x8000>; /* L1, 32K */
timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
bus-frequency = <198000000>; /* 198 MHz csb bus */
clock-frequency = <396000000>; /* 396 MHz ppc core */
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256MB at 0 */
};
mbx@20000000 {
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
};
sram@30000000 {
compatible = "fsl,mpc5121-sram";
reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
};
nfc@40000000 {
compatible = "fsl,mpc5121-nfc";
reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
interrupts = <6 8>;
#address-cells = <1>;
#size-cells = <1>;
};
localbus@80000020 {
compatible = "fsl,mpc5121-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x80000020 0x40>;
interrupts = <7 0x8>;
ranges = <0x0 0x0 0xfc000000 0x04000000>;
};
soc@80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
ranges = <0x0 0x80000000 0x400000>;
reg = <0x80000000 0x400000>;
bus-frequency = <66000000>; /* 66 MHz ips bus */
/*
* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: interrupt-controller@c00 {
compatible = "fsl,mpc5121-ipic", "fsl,ipic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0xc00 0x100>;
};
/* Watchdog timer */
wdt@900 {
compatible = "fsl,mpc5121-wdt";
reg = <0x900 0x100>;
};
/* Real time clock */
rtc@a00 {
compatible = "fsl,mpc5121-rtc";
reg = <0xa00 0x100>;
interrupts = <79 0x8 80 0x8>;
};
/* Reset module */
reset@e00 {
compatible = "fsl,mpc5121-reset";
reg = <0xe00 0x100>;
};
/* Clock control */
clock@f00 {
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
};
/* Power Management Controller */
pmc@1000{
compatible = "fsl,mpc5121-pmc";
reg = <0x1000 0x100>;
interrupts = <83 0x8>;
};
gpio@1100 {
compatible = "fsl,mpc5121-gpio";
reg = <0x1100 0x100>;
interrupts = <78 0x8>;
};
can@1300 {
compatible = "fsl,mpc5121-mscan";
reg = <0x1300 0x80>;
interrupts = <12 0x8>;
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x1380 0x80>;
interrupts = <13 0x8>;
};
sdhc@1500 {
compatible = "fsl,mpc5121-sdhc";
reg = <0x1500 0x100>;
interrupts = <8 0x8>;
};
i2c@1700 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
};
i2c@1720 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
};
i2c@1740 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
};
i2ccontrol@1760 {
compatible = "fsl,mpc5121-i2c-ctrl";
reg = <0x1760 0x8>;
};
axe@2000 {
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
};
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
};
can@2300 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2300 0x80>;
interrupts = <90 0x8>;
};
can@2380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2380 0x80>;
interrupts = <91 0x8>;
};
viu@2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
};
mdio@2800 {
compatible = "fsl,mpc5121-fec-mdio";
reg = <0x2800 0x800>;
#address-cells = <1>;
#size-cells = <0>;
};
eth0: ethernet@2800 {
device_type = "network";
compatible = "fsl,mpc5121-fec";
reg = <0x2800 0x800>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
};
/* USB1 using external ULPI PHY */
usb@3000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x3000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <43 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
};
/* USB0 using internal UTMI PHY */
usb@4000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x4000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
};
/* IO control */
ioctl@a000 {
compatible = "fsl,mpc5121-ioctl";
reg = <0xA000 0x1000>;
};
/* LocalPlus controller */
lpc@10000 {
compatible = "fsl,mpc5121-lpc";
reg = <0x10000 0x200>;
};
pata@10200 {
compatible = "fsl,mpc5121-pata";
reg = <0x10200 0x100>;
interrupts = <5 0x8>;
};
/* 512x PSCs are not 52xx PSC compatible */
/* PSC0 */
psc@11000 {
compatible = "fsl,mpc5121-psc";
reg = <0x11000 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC1 */
psc@11100 {
compatible = "fsl,mpc5121-psc";
reg = <0x11100 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC2 */
psc@11200 {
compatible = "fsl,mpc5121-psc";
reg = <0x11200 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC3 */
psc@11300 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
reg = <0x11300 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC4 */
psc@11400 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
reg = <0x11400 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC5 */
psc@11500 {
compatible = "fsl,mpc5121-psc";
reg = <0x11500 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC6 */
psc@11600 {
compatible = "fsl,mpc5121-psc";
reg = <0x11600 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC7 */
psc@11700 {
compatible = "fsl,mpc5121-psc";
reg = <0x11700 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC8 */
psc@11800 {
compatible = "fsl,mpc5121-psc";
reg = <0x11800 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC9 */
psc@11900 {
compatible = "fsl,mpc5121-psc";
reg = <0x11900 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC10 */
psc@11a00 {
compatible = "fsl,mpc5121-psc";
reg = <0x11a00 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
/* PSC11 */
psc@11b00 {
compatible = "fsl,mpc5121-psc";
reg = <0x11b00 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
pscfifo@11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
};
dma@14000 {
compatible = "fsl,mpc5121-dma";
reg = <0x14000 0x1800>;
interrupts = <65 0x8>;
};
};
pci: pci@80008500 {
compatible = "fsl,mpc5121-pci";
device_type = "pci";
interrupts = <1 0x8>;
clock-frequency = <0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
reg = <0x80008500 0x100 /* internal registers */
0x80008300 0x8>; /* config space access registers */
bus-range = <0x0 0x0>;
ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
};
};

319
arch/powerpc/boot/dts/mpc5121ads.dts
View File

@ -1,7 +1,7 @@
/*
* MPC5121E ADS Device Tree Source
*
* Copyright 2007,2008 Freescale Semiconductor Inc.
* Copyright 2007-2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,74 +9,26 @@
* option) any later version.
*/
/dts-v1/;
/include/ "mpc5121.dtsi"
/ {
model = "mpc5121ads";
compatible = "fsl,mpc5121ads";
#address-cells = <1>;
#size-cells = <1>;
aliases {
pci = &pci;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5121@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <0x20>; // 32 bytes
i-cache-line-size = <0x20>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
bus-frequency = <198000000>; // 198 MHz csb bus
clock-frequency = <396000000>; // 396 MHz ppc core
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; // 256MB at 0
};
mbx@20000000 {
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
interrupt-parent = < &ipic >;
};
sram@30000000 {
compatible = "fsl,mpc5121-sram";
reg = <0x30000000 0x20000>; // 128K at 0x30000000
};
nfc@40000000 {
compatible = "fsl,mpc5121-nfc";
reg = <0x40000000 0x100000>; // 1M at 0x40000000
interrupts = <6 8>;
interrupt-parent = < &ipic >;
#address-cells = <1>;
#size-cells = <1>;
// ADS has two Hynix 512MB Nand flash chips in a single
// stacked package.
/*
* ADS has two Hynix 512MB Nand flash chips in a single
* stacked package.
*/
chips = <2>;
nand@0 {
label = "nand";
reg = <0x00000000 0x40000000>; // 512MB + 512MB
reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
};
};
localbus@80000020 {
compatible = "fsl,mpc5121-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x80000020 0x40>;
ranges = <0x0 0x0 0xfc000000 0x04000000
0x2 0x0 0x82000000 0x00008000>;
@ -87,6 +39,7 @@
#size-cells = <1>;
bank-width = <4>;
device-width = <2>;
protected@0 {
label = "protected";
reg = <0x00000000 0x00040000>; // first sector is protected
@ -121,91 +74,18 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2 0xa 0x5>;
interrupt-parent = < &ipic >;
// irq routing
// all irqs but touch screen are routed to irq0 (ipic 48)
// touch screen is statically routed to irq1 (ipic 17)
// so don't use it here
/* irq routing:
* all irqs but touch screen are routed to irq0 (ipic 48)
* touch screen is statically routed to irq1 (ipic 17)
* so don't use it here
*/
interrupts = <48 0x8>;
};
};
soc@80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
ranges = <0x0 0x80000000 0x400000>;
reg = <0x80000000 0x400000>;
bus-frequency = <66000000>; // 66 MHz ips bus
// IPIC
// interrupts cell = <intr #, sense>
// sense values match linux IORESOURCE_IRQ_* defines:
// sense == 8: Level, low assertion
// sense == 2: Edge, high-to-low change
//
ipic: interrupt-controller@c00 {
compatible = "fsl,mpc5121-ipic", "fsl,ipic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0xc00 0x100>;
};
rtc@a00 { // Real time clock
compatible = "fsl,mpc5121-rtc";
reg = <0xa00 0x100>;
interrupts = <79 0x8 80 0x8>;
interrupt-parent = < &ipic >;
};
reset@e00 { // Reset module
compatible = "fsl,mpc5121-reset";
reg = <0xe00 0x100>;
};
clock@f00 { // Clock control
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
};
pmc@1000{ //Power Management Controller
compatible = "fsl,mpc5121-pmc";
reg = <0x1000 0x100>;
interrupts = <83 0x2>;
interrupt-parent = < &ipic >;
};
gpio@1100 {
compatible = "fsl,mpc5121-gpio";
reg = <0x1100 0x100>;
interrupts = <78 0x8>;
interrupt-parent = < &ipic >;
};
can@1300 {
compatible = "fsl,mpc5121-mscan";
interrupts = <12 0x8>;
interrupt-parent = < &ipic >;
reg = <0x1300 0x80>;
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
interrupts = <13 0x8>;
interrupt-parent = < &ipic >;
reg = <0x1380 0x80>;
};
i2c@1700 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
interrupt-parent = < &ipic >;
fsl,preserve-clocking;
hwmon@4a {
@ -224,196 +104,75 @@
};
};
i2c@1720 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
interrupt-parent = < &ipic >;
eth0: ethernet@2800 {
phy-handle = <&phy0>;
};
i2c@1740 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
interrupt-parent = < &ipic >;
can@2300 {
status = "disabled";
};
i2ccontrol@1760 {
compatible = "fsl,mpc5121-i2c-ctrl";
reg = <0x1760 0x8>;
can@2380 {
status = "disabled";
};
axe@2000 {
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
interrupt-parent = < &ipic >;
};
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
interrupt-parent = < &ipic >;
viu@2400 {
status = "disabled";
};
mdio@2800 {
compatible = "fsl,mpc5121-fec-mdio";
reg = <0x2800 0x800>;
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
phy0: ethernet-phy@0 {
reg = <1>;
device_type = "ethernet-phy";
};
};
ethernet@2800 {
device_type = "network";
compatible = "fsl,mpc5121-fec";
reg = <0x2800 0x800>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy >;
fsl,align-tx-packets = <4>;
/* mpc5121ads only uses USB0 */
usb@3000 {
status = "disabled";
};
// 5121e has two dr usb modules
// mpc5121_ads only uses USB0
// USB1 using external ULPI PHY
//usb@3000 {
// compatible = "fsl,mpc5121-usb2-dr";
// reg = <0x3000 0x1000>;
// #address-cells = <1>;
// #size-cells = <0>;
// interrupt-parent = < &ipic >;
// interrupts = <43 0x8>;
// dr_mode = "otg";
// phy_type = "ulpi";
//};
// USB0 using internal UTMI PHY
/* USB0 using internal UTMI PHY */
usb@4000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x4000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = < &ipic >;
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
dr_mode = "host";
fsl,invert-drvvbus;
fsl,invert-pwr-fault;
};
// IO control
ioctl@a000 {
compatible = "fsl,mpc5121-ioctl";
reg = <0xA000 0x1000>;
};
pata@10200 {
compatible = "fsl,mpc5121-pata";
reg = <0x10200 0x100>;
interrupts = <5 0x8>;
interrupt-parent = < &ipic >;
};
// 512x PSCs are not 52xx PSC compatible
// PSC3 serial port A aka ttyPSC0
serial@11300 {
device_type = "serial";
/* PSC3 serial port A aka ttyPSC0 */
psc@11300 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
// Logical port assignment needed until driver
// learns to use aliases
port-number = <0>;
cell-index = <3>;
reg = <0x11300 0x100>;
interrupts = <40 0x8>;
interrupt-parent = < &ipic >;
rx-fifo-size = <16>;
tx-fifo-size = <16>;
};
// PSC4 serial port B aka ttyPSC1
serial@11400 {
device_type = "serial";
/* PSC4 serial port B aka ttyPSC1 */
psc@11400 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
// Logical port assignment needed until driver
// learns to use aliases
port-number = <1>;
cell-index = <4>;
reg = <0x11400 0x100>;
interrupts = <40 0x8>;
interrupt-parent = < &ipic >;
rx-fifo-size = <16>;
tx-fifo-size = <16>;
};
// PSC5 in ac97 mode
ac97@11500 {
/* PSC5 in ac97 mode */
ac97: psc@11500 {
compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
cell-index = <5>;
reg = <0x11500 0x100>;
interrupts = <40 0x8>;
interrupt-parent = < &ipic >;
fsl,mode = "ac97-slave";
rx-fifo-size = <384>;
tx-fifo-size = <384>;
fsl,rx-fifo-size = <384>;
fsl,tx-fifo-size = <384>;
};
pscfifo@11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
interrupt-parent = < &ipic >;
};
dma@14000 {
compatible = "fsl,mpc5121-dma";
reg = <0x14000 0x1800>;
interrupts = <65 0x8>;
interrupt-parent = < &ipic >;
};
};
pci: pci@80008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
// IDSEL 0x15 - Slot 1 PCI
/* IDSEL 0x15 - Slot 1 PCI */
0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
// IDSEL 0x16 - Slot 2 MiniPCI
/* IDSEL 0x16 - Slot 2 MiniPCI */
0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
// IDSEL 0x17 - Slot 3 MiniPCI
/* IDSEL 0x17 - Slot 3 MiniPCI */
0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
>;
interrupt-parent = < &ipic >;
interrupts = <1 0x8>;
bus-range = <0 0>;
ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0x80008500 0x100 /* internal registers */
0x80008300 0x8>; /* config space access registers */
compatible = "fsl,mpc5121-pci";
device_type = "pci";
};
};

25
arch/powerpc/boot/dts/mpc5200b.dtsi
View File

@ -64,50 +64,59 @@
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
gpt0: timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
#gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
reg = <0x600 0x10>;
interrupts = <1 9 0>;
// add 'fsl,has-wdt' to enable watchdog
};
timer@610 { // General Purpose Timer
gpt1: timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
#gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
reg = <0x610 0x10>;
interrupts = <1 10 0>;
};
timer@620 { // General Purpose Timer
gpt2: timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
#gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
reg = <0x620 0x10>;
interrupts = <1 11 0>;
};
timer@630 { // General Purpose Timer
gpt3: timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
#gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
reg = <0x630 0x10>;
interrupts = <1 12 0>;
};
timer@640 { // General Purpose Timer
gpt4: timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
#gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
reg = <0x640 0x10>;
interrupts = <1 13 0>;
};
timer@650 { // General Purpose Timer
gpt5: timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
#gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
reg = <0x650 0x10>;
interrupts = <1 14 0>;
};
timer@660 { // General Purpose Timer
gpt6: timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
#gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
reg = <0x660 0x10>;
interrupts = <1 15 0>;
};
timer@670 { // General Purpose Timer
gpt7: timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
#gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
reg = <0x670 0x10>;
interrupts = <1 16 0>;
};

48
arch/powerpc/boot/dts/mucmc52.dts
View File

@ -13,47 +13,23 @@
/include/ "mpc5200b.dtsi"
/* Timer pins that need to be in GPIO mode */
&gpt0 { gpio-controller; };
&gpt1 { gpio-controller; };
&gpt2 { gpio-controller; };
&gpt3 { gpio-controller; };
/* Disabled timers */
&gpt4 { status = "disabled"; };
&gpt5 { status = "disabled"; };
&gpt6 { status = "disabled"; };
&gpt7 { status = "disabled"; };
/ {
model = "manroland,mucmc52";
compatible = "manroland,mucmc52";
soc5200@f0000000 {
gpt0: timer@600 { // GPT 0 in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt1: timer@610 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
timer@640 {
status = "disabled";
};
timer@650 {
status = "disabled";
};
timer@660 {
status = "disabled";
};
timer@670 {
status = "disabled";
};
rtc@800 {
status = "disabled";
};

27
arch/powerpc/boot/dts/o2d.dtsi
View File

@ -12,6 +12,13 @@
/include/ "mpc5200b.dtsi"
&gpt0 {
gpio-controller;
fsl,has-wdt;
fsl,wdt-on-boot = <0>;
};
&gpt1 { gpio-controller; };
/ {
model = "ifm,o2d";
compatible = "ifm,o2d";
@ -22,24 +29,6 @@
soc5200@f0000000 {
gpio_simple: gpio@b00 {
};
timer@600 { // General Purpose Timer
#gpio-cells = <2>;
gpio-controller;
fsl,has-wdt;
fsl,wdt-on-boot = <0>;
};
timer@610 {
#gpio-cells = <2>;
gpio-controller;
};
timer7: timer@670 {
};
rtc@800 {
status = "disabled";
};
@ -118,7 +107,7 @@
csi@3,0 {
compatible = "ifm,o2d-csi";
reg = <3 0 0x00100000>;
ifm,csi-clk-handle = <&timer7>;
ifm,csi-clk-handle = <&gpt7>;
gpios = <&gpio_simple 23 0 /* imag_capture */
&gpio_simple 26 0 /* imag_reset */
&gpio_simple 29 0>; /* imag_master_en */

48
arch/powerpc/boot/dts/pcm030.dts
View File

@ -14,51 +14,19 @@
/include/ "mpc5200b.dtsi"
&gpt0 { fsl,has-wdt; };
&gpt2 { gpio-controller; };
&gpt3 { gpio-controller; };
&gpt4 { gpio-controller; };
&gpt5 { gpio-controller; };
&gpt6 { gpio-controller; };
&gpt7 { gpio-controller; };
/ {
model = "phytec,pcm030";
compatible = "phytec,pcm030";
soc5200@f0000000 {
timer@600 { // General Purpose Timer
fsl,has-wdt;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt6: timer@660 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt7: timer@670 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
audioplatform: psc@2000 { /* PSC1 in ac97 mode */
compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
cell-index = <0>;

45
arch/powerpc/boot/dts/pcm032.dts
View File

@ -14,6 +14,14 @@
/include/ "mpc5200b.dtsi"
&gpt0 { fsl,has-wdt; };
&gpt2 { gpio-controller; };
&gpt3 { gpio-controller; };
&gpt4 { gpio-controller; };
&gpt5 { gpio-controller; };
&gpt6 { gpio-controller; };
&gpt7 { gpio-controller; };
/ {
model = "phytec,pcm032";
compatible = "phytec,pcm032";
@ -23,43 +31,6 @@
};
soc5200@f0000000 {
timer@600 { // General Purpose Timer
fsl,has-wdt;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt6: timer@660 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt7: timer@670 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
psc@2000 { /* PSC1 is ac97 */
compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
cell-index = <0>;

279
arch/powerpc/boot/dts/pdm360ng.dts
View File

@ -13,7 +13,7 @@
* option) any later version.
*/
/dts-v1/;
/include/ "mpc5121.dtsi"
/ {
model = "pdm360ng";
@ -22,38 +22,12 @@
#size-cells = <1>;
interrupt-parent = <&ipic>;
aliases {
ethernet0 = &eth0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5121@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <0x20>; // 32 bytes
i-cache-line-size = <0x20>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
bus-frequency = <198000000>; // 198 MHz csb bus
clock-frequency = <396000000>; // 396 MHz ppc core
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512MB at 0
};
nfc@40000000 {
compatible = "fsl,mpc5121-nfc";
reg = <0x40000000 0x100000>;
interrupts = <0x6 0x8>;
#address-cells = <0x1>;
#size-cells = <0x1>;
bank-width = <0x1>;
chips = <0x1>;
@ -63,17 +37,7 @@
};
};
sram@50000000 {
compatible = "fsl,mpc5121-sram";
reg = <0x50000000 0x20000>; // 128K at 0x50000000
};
localbus@80000020 {
compatible = "fsl,mpc5121-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x80000020 0x40>;
ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
@ -129,74 +93,8 @@
};
soc@80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
ranges = <0x0 0x80000000 0x400000>;
reg = <0x80000000 0x400000>;
bus-frequency = <66000000>; // 66 MHz ips bus
// IPIC
// interrupts cell = <intr #, sense>
// sense values match linux IORESOURCE_IRQ_* defines:
// sense == 8: Level, low assertion
// sense == 2: Edge, high-to-low change
//
ipic: interrupt-controller@c00 {
compatible = "fsl,mpc5121-ipic", "fsl,ipic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0xc00 0x100>;
};
rtc@a00 { // Real time clock
compatible = "fsl,mpc5121-rtc";
reg = <0xa00 0x100>;
interrupts = <79 0x8 80 0x8>;
};
reset@e00 { // Reset module
compatible = "fsl,mpc5121-reset";
reg = <0xe00 0x100>;
};
clock@f00 { // Clock control
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
};
pmc@1000{ //Power Management Controller
compatible = "fsl,mpc5121-pmc";
reg = <0x1000 0x100>;
interrupts = <83 0x2>;
};
gpio@1100 {
compatible = "fsl,mpc5121-gpio";
reg = <0x1100 0x100>;
interrupts = <78 0x8>;
};
can@1300 {
compatible = "fsl,mpc5121-mscan";
interrupts = <12 0x8>;
reg = <0x1300 0x80>;
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
interrupts = <13 0x8>;
reg = <0x1380 0x80>;
};
i2c@1700 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c";
reg = <0x1700 0x20>;
interrupts = <0x9 0x8>;
fsl,preserve-clocking;
eeprom@50 {
@ -210,201 +108,92 @@
};
};
i2c@1720 {
status = "disabled";
};
i2c@1740 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c";
reg = <0x1740 0x20>;
interrupts = <0xb 0x8>;
fsl,preserve-clocking;
};
i2ccontrol@1760 {
compatible = "fsl,mpc5121-i2c-ctrl";
reg = <0x1760 0x8>;
};
axe@2000 {
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
};
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
};
can@2300 {
compatible = "fsl,mpc5121-mscan";
interrupts = <90 0x8>;
reg = <0x2300 0x80>;
};
can@2380 {
compatible = "fsl,mpc5121-mscan";
interrupts = <91 0x8>;
reg = <0x2380 0x80>;
};
viu@2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
ethernet@2800 {
phy-handle = <&phy0>;
};
mdio@2800 {
compatible = "fsl,mpc5121-fec-mdio";
reg = <0x2800 0x200>;
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
phy0: ethernet-phy@1f {
compatible = "smsc,lan8700";
reg = <0x1f>;
};
};
eth0: ethernet@2800 {
compatible = "fsl,mpc5121-fec";
reg = <0x2800 0x200>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
phy-handle = < &phy >;
};
// USB1 using external ULPI PHY
/* USB1 using external ULPI PHY */
usb@3000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x3000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <43 0x8>;
dr_mode = "host";
phy_type = "ulpi";
};
// USB0 using internal UTMI PHY
/* USB0 using internal UTMI PHY */
usb@4000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x4000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
fsl,invert-pwr-fault;
};
// IO control
ioctl@a000 {
compatible = "fsl,mpc5121-ioctl";
reg = <0xA000 0x1000>;
};
// 512x PSCs are not 52xx PSCs compatible
serial@11000 {
psc@11000 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <0>;
reg = <0x11000 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11100 {
psc@11100 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <1>;
reg = <0x11100 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11200 {
psc@11200 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <2>;
reg = <0x11200 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11300 {
psc@11300 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <3>;
reg = <0x11300 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11400 {
psc@11400 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <4>;
reg = <0x11400 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11600 {
psc@11500 {
status = "disabled";
};
psc@11600 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <6>;
reg = <0x11600 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11800 {
psc@11700 {
status = "disabled";
};
psc@11800 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <8>;
reg = <0x11800 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11B00 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <11>;
reg = <0x11B00 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
pscfifo@11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
};
spi@11900 {
psc@11900 {
compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
cell-index = <9>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x11900 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
// 7845 touch screen controller
/* ADS7845 touch screen controller */
ts@0 {
compatible = "ti,ads7846";
reg = <0x0>;
spi-max-frequency = <3000000>;
// pen irq is GPIO25
/* pen irq is GPIO25 */
interrupts = <78 0x8>;
};
};
dma@14000 {
compatible = "fsl,mpc5121-dma";
reg = <0x14000 0x1800>;
interrupts = <65 0x8>;
psc@11a00 {
status = "disabled";
};
psc@11b00 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
};
};
};

52
arch/powerpc/boot/dts/uc101.dts
View File

@ -13,54 +13,20 @@
/include/ "mpc5200b.dtsi"
&gpt0 { gpio-controller; };
&gpt1 { gpio-controller; };
&gpt2 { gpio-controller; };
&gpt3 { gpio-controller; };
&gpt4 { gpio-controller; };
&gpt5 { gpio-controller; };
&gpt6 { gpio-controller; };
&gpt7 { gpio-controller; };
/ {
model = "manroland,uc101";
compatible = "manroland,uc101";
soc5200@f0000000 {
gpt0: timer@600 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt1: timer@610 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt6: timer@660 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
gpt7: timer@670 { // General Purpose Timer in GPIO mode
gpio-controller;
#gpio-cells = <2>;
};
rtc@800 {
status = "disabled";
};

17
arch/powerpc/include/asm/mpc5121.h
View File

@ -53,4 +53,21 @@ struct mpc512x_ccm {
u32 m4ccr; /* MSCAN4 CCR */
u8 res[0x98]; /* Reserved */
};
/*
* LPC Module
*/
struct mpc512x_lpc {
u32 cs_cfg[8]; /* CS config */
u32 cs_ctrl; /* CS Control Register */
u32 cs_status; /* CS Status Register */
u32 burst_ctrl; /* CS Burst Control Register */
u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
u32 alt; /* Address Latch Timing Register */
};
int mpc512x_cs_config(unsigned int cs, u32 val);
int __init mpc5121_clk_init(void);
#endif /* __ASM_POWERPC_MPC5121_H__ */

34
arch/powerpc/platforms/512x/clock.c
View File

@ -26,6 +26,7 @@
#include <linux/of_platform.h>
#include <asm/mpc5xxx.h>
#include <asm/mpc5121.h>
#include <asm/clk_interface.h>
#undef CLK_DEBUG
@ -122,7 +123,7 @@ struct mpc512x_clockctl {
u32 dccr; /* DIU Clk Cnfg Reg */
};
struct mpc512x_clockctl __iomem *clockctl;
static struct mpc512x_clockctl __iomem *clockctl;
static int mpc5121_clk_enable(struct clk *clk)
{
@ -184,7 +185,7 @@ static unsigned long spmf_mult(void)
36, 40, 44, 48,
52, 56, 60, 64
};
int spmf = (clockctl->spmr >> 24) & 0xf;
int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
return spmf_to_mult[spmf];
}
@ -206,7 +207,7 @@ static unsigned long sysdiv_div_x_2(void)
52, 56, 58, 62,
60, 64, 66,
};
int sysdiv = (clockctl->scfr2 >> 26) & 0x3f;
int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
return sysdiv_to_div_x_2[sysdiv];
}
@ -230,7 +231,7 @@ static unsigned long sys_to_ref(unsigned long rate)
static long ips_to_ref(unsigned long rate)
{
int ips_div = (clockctl->scfr1 >> 23) & 0x7;
int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
rate *= ips_div; /* csb_clk = ips_clk * ips_div */
rate *= 2; /* sys_clk = csb_clk * 2 */
@ -284,7 +285,7 @@ static struct clk sys_clk = {
static void diu_clk_calc(struct clk *clk)
{
int diudiv_x_2 = clockctl->scfr1 & 0xff;
int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
unsigned long rate;
rate = sys_clk.rate;
@ -311,7 +312,7 @@ static void half_clk_calc(struct clk *clk)
static void generic_div_clk_calc(struct clk *clk)
{
int div = (clockctl->scfr1 >> clk->div_shift) & 0x7;
int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
clk->rate = clk->parent->rate / div;
}
@ -329,7 +330,7 @@ static struct clk csb_clk = {
static void e300_clk_calc(struct clk *clk)
{
int spmf = (clockctl->spmr >> 16) & 0xf;
int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
int ratex2 = clk->parent->rate * spmf;
clk->rate = ratex2 / 2;
@ -551,7 +552,7 @@ static struct clk ac97_clk = {
.calc = ac97_clk_calc,
};
struct clk *rate_clks[] = {
static struct clk *rate_clks[] = {
&ref_clk,
&sys_clk,
&diu_clk,
@ -607,7 +608,7 @@ static void rate_clks_init(void)
* There are two clk enable registers with 32 enable bits each
* psc clocks and device clocks are all stored in dev_clks
*/
struct clk dev_clks[2][32];
static struct clk dev_clks[2][32];
/*
* Given a psc number return the dev_clk
@ -648,12 +649,12 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
out_be32(&clockctl->pccr[pscnum], 0x00020000);
out_be32(&clockctl->pccr[pscnum], 0x00030000);
if (clockctl->pccr[pscnum] & 0x80) {
if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
clk->rate = spdif_rxclk.rate;
return;
}
switch ((clockctl->pccr[pscnum] >> 14) & 0x3) {
switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
case 0:
mclk_src = sys_clk.rate;
break;
@ -668,7 +669,7 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
break;
}
mclk_div = ((clockctl->pccr[pscnum] >> 17) & 0x7fff) + 1;
mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
clk->rate = mclk_src / mclk_div;
}
@ -680,13 +681,12 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
static void psc_clks_init(void)
{
struct device_node *np;
const u32 *cell_index;
struct platform_device *ofdev;
u32 reg;
for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
cell_index = of_get_property(np, "cell-index", NULL);
if (cell_index) {
int pscnum = *cell_index;
if (!of_property_read_u32(np, "reg", &reg)) {
int pscnum = (reg & 0xf00) >> 8;
struct clk *clk = psc_dev_clk(pscnum);
clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
@ -696,7 +696,7 @@ static void psc_clks_init(void)
* AC97 is special rate clock does
* not go through normal path
*/
if (strcmp("ac97", np->name) == 0)
if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
clk->rate = ac97_clk.rate;
else
psc_calc_rate(clk, pscnum, np);

32
arch/powerpc/platforms/512x/mpc512x_shared.c
View File

@ -426,8 +426,38 @@ void __init mpc512x_psc_fifo_init(void)
void __init mpc512x_init(void)
{
mpc512x_declare_of_platform_devices();
mpc5121_clk_init();
mpc512x_declare_of_platform_devices();
mpc512x_restart_init();
mpc512x_psc_fifo_init();
}
/**
* mpc512x_cs_config - Setup chip select configuration
* @cs: chip select number
* @val: chip select configuration value
*
* Perform chip select configuration for devices on LocalPlus Bus.
* Intended to dynamically reconfigure the chip select parameters
* for configurable devices on the bus.
*/
int mpc512x_cs_config(unsigned int cs, u32 val)
{
static struct mpc512x_lpc __iomem *lpc;
struct device_node *np;
if (cs > 7)
return -EINVAL;
if (!lpc) {
np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-lpc");
lpc = of_iomap(np, 0);
of_node_put(np);
if (!lpc)
return -ENOMEM;
}
out_be32(&lpc->cs_cfg[cs], val);
return 0;
}
EXPORT_SYMBOL(mpc512x_cs_config);

6
arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
View File

@ -20,9 +20,9 @@
#include <asm/mpc52xx.h>
#include <asm/time.h>
#include <sysdev/bestcomm/bestcomm.h>
#include <sysdev/bestcomm/bestcomm_priv.h>
#include <sysdev/bestcomm/gen_bd.h>
#include <linux/fsl/bestcomm/bestcomm.h>
#include <linux/fsl/bestcomm/bestcomm_priv.h>
#include <linux/fsl/bestcomm/gen_bd.h>
MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver");

2
arch/powerpc/platforms/Kconfig
View File

@ -352,8 +352,6 @@ config OF_RTC
Uses information from the OF or flattened device tree to instantiate
platform devices for direct mapped RTC chips like the DS1742 or DS1743.
source "arch/powerpc/sysdev/bestcomm/Kconfig"
config SIMPLE_GPIO
bool "Support for simple, memory-mapped GPIO controllers"
depends on PPC

1
arch/powerpc/sysdev/Makefile
View File

@ -26,7 +26,6 @@ obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
mv64x60_udbg.o

4
arch/powerpc/sysdev/mpc5xxx_clocks.c
View File

@ -9,9 +9,9 @@
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/export.h>
#include <asm/mpc5xxx.h>
unsigned int
mpc5xxx_get_bus_frequency(struct device_node *node)
unsigned long mpc5xxx_get_bus_frequency(struct device_node *node)
{
struct device_node *np;
const unsigned int *p_bus_freq = NULL;

2
drivers/Makefile
View File

@ -29,7 +29,7 @@ obj-$(CONFIG_PNP) += pnp/
obj-y += amba/
# Many drivers will want to use DMA so this has to be made available
# really early.
obj-$(CONFIG_DMA_ENGINE) += dma/
obj-$(CONFIG_DMADEVICES) += dma/
obj-$(CONFIG_VIRTIO) += virtio/
obj-$(CONFIG_XEN) += xen/

6
drivers/ata/pata_mpc52xx.c
View File

@ -26,9 +26,9 @@
#include <asm/prom.h>
#include <asm/mpc52xx.h>
#include <sysdev/bestcomm/bestcomm.h>
#include <sysdev/bestcomm/bestcomm_priv.h>
#include <sysdev/bestcomm/ata.h>
#include <linux/fsl/bestcomm/bestcomm.h>
#include <linux/fsl/bestcomm/bestcomm_priv.h>
#include <linux/fsl/bestcomm/ata.h>
#define DRV_NAME "mpc52xx_ata"

2
drivers/dma/Kconfig
View File

@ -125,6 +125,8 @@ config MPC512X_DMA
---help---
Enable support for the Freescale MPC512x built-in DMA engine.
source "drivers/dma/bestcomm/Kconfig"
config MV_XOR
bool "Marvell XOR engine support"
depends on PLAT_ORION

1
drivers/dma/Makefile
View File

@ -10,6 +10,7 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioat/
obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
obj-$(CONFIG_MV_XOR) += mv_xor.o
obj-$(CONFIG_DW_DMAC) += dw_dmac.o
obj-$(CONFIG_AT_HDMAC) += at_hdmac.o

0
arch/powerpc/sysdev/bestcomm/Kconfig → drivers/dma/bestcomm/Kconfig
View File

0
arch/powerpc/sysdev/bestcomm/Makefile → drivers/dma/bestcomm/Makefile
View File

6
arch/powerpc/sysdev/bestcomm/ata.c → drivers/dma/bestcomm/ata.c
View File

@ -18,9 +18,9 @@
#include <linux/types.h>
#include <asm/io.h>
#include "bestcomm.h"
#include "bestcomm_priv.h"
#include "ata.h"
#include <linux/fsl/bestcomm/bestcomm.h>
#include <linux/fsl/bestcomm/bestcomm_priv.h>
#include <linux/fsl/bestcomm/ata.h>
/* ======================================================================== */

0
arch/powerpc/sysdev/bestcomm/bcom_ata_task.c → drivers/dma/bestcomm/bcom_ata_task.c
View File

0
arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c → drivers/dma/bestcomm/bcom_fec_rx_task.c
View File

0
arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c → drivers/dma/bestcomm/bcom_fec_tx_task.c
View File

0
arch/powerpc/sysdev/bestcomm/bcom_gen_bd_rx_task.c → drivers/dma/bestcomm/bcom_gen_bd_rx_task.c
View File

0
arch/powerpc/sysdev/bestcomm/bcom_gen_bd_tx_task.c → drivers/dma/bestcomm/bcom_gen_bd_tx_task.c
View File

6
arch/powerpc/sysdev/bestcomm/bestcomm.c → drivers/dma/bestcomm/bestcomm.c
View File

@ -23,9 +23,9 @@
#include <asm/irq.h>
#include <asm/mpc52xx.h>
#include "sram.h"
#include "bestcomm_priv.h"
#include "bestcomm.h"
#include <linux/fsl/bestcomm/sram.h>
#include <linux/fsl/bestcomm/bestcomm_priv.h>
#include "linux/fsl/bestcomm/bestcomm.h"
#define DRIVER_NAME "bestcomm-core"

6
arch/powerpc/sysdev/bestcomm/fec.c → drivers/dma/bestcomm/fec.c
View File

@ -16,9 +16,9 @@
#include <linux/types.h>
#include <asm/io.h>
#include "bestcomm.h"
#include "bestcomm_priv.h"
#include "fec.h"
#include <linux/fsl/bestcomm/bestcomm.h>
#include <linux/fsl/bestcomm/bestcomm_priv.h>
#include <linux/fsl/bestcomm/fec.h>
/* ======================================================================== */

6
arch/powerpc/sysdev/bestcomm/gen_bd.c → drivers/dma/bestcomm/gen_bd.c
View File

@ -21,9 +21,9 @@
#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>
#include "bestcomm.h"
#include "bestcomm_priv.h"
#include "gen_bd.h"
#include <linux/fsl/bestcomm/bestcomm.h>
#include <linux/fsl/bestcomm/bestcomm_priv.h>
#include <linux/fsl/bestcomm/gen_bd.h>
/* ======================================================================== */

2
arch/powerpc/sysdev/bestcomm/sram.c → drivers/dma/bestcomm/sram.c
View File

@ -23,7 +23,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include "sram.h"
#include <linux/fsl/bestcomm/sram.h>
/* Struct keeping our 'state' */

4
drivers/net/ethernet/freescale/fec_mpc52xx.c
View File

@ -40,8 +40,8 @@
#include <asm/delay.h>
#include <asm/mpc52xx.h>
#include <sysdev/bestcomm/bestcomm.h>
#include <sysdev/bestcomm/fec.h>
#include <linux/fsl/bestcomm/bestcomm.h>
#include <linux/fsl/bestcomm/fec.h>
#include "fec_mpc52xx.h"

64
drivers/video/fsl-diu-fb.c
View File

@ -944,7 +944,7 @@ static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
#define PF_COMP_0_MASK 0x0000000F
#define PF_COMP_0_SHIFT 0
#define MAKE_PF(alpha, red, blue, green, size, c0, c1, c2, c3) \
#define MAKE_PF(alpha, red, green, blue, size, c0, c1, c2, c3) \
cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \
(blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \
(red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \
@ -954,10 +954,10 @@ static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
switch (bits_per_pixel) {
case 32:
/* 0x88883316 */
return MAKE_PF(3, 2, 0, 1, 3, 8, 8, 8, 8);
return MAKE_PF(3, 2, 1, 0, 3, 8, 8, 8, 8);
case 24:
/* 0x88082219 */
return MAKE_PF(4, 0, 1, 2, 2, 0, 8, 8, 8);
return MAKE_PF(4, 0, 1, 2, 2, 8, 8, 8, 0);
case 16:
/* 0x65053118 */
return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0);
@ -1232,6 +1232,16 @@ static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
return 0;
}
static inline void fsl_diu_enable_interrupts(struct fsl_diu_data *data)
{
u32 int_mask = INT_UNDRUN; /* enable underrun detection */
if (IS_ENABLED(CONFIG_NOT_COHERENT_CACHE))
int_mask |= INT_VSYNC; /* enable vertical sync */
clrbits32(&data->diu_reg->int_mask, int_mask);
}
/* turn on fb if count == 1
*/
static int fsl_diu_open(struct fb_info *info, int user)
@ -1251,19 +1261,7 @@ static int fsl_diu_open(struct fb_info *info, int user)
if (res < 0)
mfbi->count--;
else {
struct fsl_diu_data *data = mfbi->parent;
#ifdef CONFIG_NOT_COHERENT_CACHE
/*
* Enable underrun detection and vertical sync
* interrupts.
*/
clrbits32(&data->diu_reg->int_mask,
INT_UNDRUN | INT_VSYNC);
#else
/* Enable underrun detection */
clrbits32(&data->diu_reg->int_mask, INT_UNDRUN);
#endif
fsl_diu_enable_interrupts(mfbi->parent);
fsl_diu_enable_panel(info);
}
}
@ -1283,9 +1281,18 @@ static int fsl_diu_release(struct fb_info *info, int user)
mfbi->count--;
if (mfbi->count == 0) {
struct fsl_diu_data *data = mfbi->parent;
bool disable = true;
int i;
/* Disable interrupts */
out_be32(&data->diu_reg->int_mask, 0xffffffff);
/* Disable interrupts only if all AOIs are closed */
for (i = 0; i < NUM_AOIS; i++) {
struct mfb_info *mi = data->fsl_diu_info[i].par;
if (mi->count)
disable = false;
}
if (disable)
out_be32(&data->diu_reg->int_mask, 0xffffffff);
fsl_diu_disable_panel(info);
}
@ -1614,14 +1621,6 @@ static int fsl_diu_probe(struct platform_device *pdev)
out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr);
out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr);
for (i = 0; i < NUM_AOIS; i++) {
ret = install_fb(&data->fsl_diu_info[i]);
if (ret) {
dev_err(&pdev->dev, "could not register fb %d\n", i);
goto error;
}
}
/*
* Older versions of U-Boot leave interrupts enabled, so disable
* all of them and clear the status register.
@ -1630,12 +1629,21 @@ static int fsl_diu_probe(struct platform_device *pdev)
in_be32(&data->diu_reg->int_status);
ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb",
&data->diu_reg);
data->diu_reg);
if (ret) {
dev_err(&pdev->dev, "could not claim irq\n");
goto error;
}
for (i = 0; i < NUM_AOIS; i++) {
ret = install_fb(&data->fsl_diu_info[i]);
if (ret) {
dev_err(&pdev->dev, "could not register fb %d\n", i);
free_irq(data->irq, data->diu_reg);
goto error;
}
}
sysfs_attr_init(&data->dev_attr.attr);
data->dev_attr.attr.name = "monitor";
data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
@ -1667,7 +1675,7 @@ static int fsl_diu_remove(struct platform_device *pdev)
data = dev_get_drvdata(&pdev->dev);
disable_lcdc(&data->fsl_diu_info[0]);
free_irq(data->irq, &data->diu_reg);
free_irq(data->irq, data->diu_reg);
for (i = 0; i < NUM_AOIS; i++)
uninstall_fb(&data->fsl_diu_info[i]);

0
arch/powerpc/sysdev/bestcomm/ata.h → include/linux/fsl/bestcomm/ata.h
View File

0
arch/powerpc/sysdev/bestcomm/bestcomm.h → include/linux/fsl/bestcomm/bestcomm.h
View File

0
arch/powerpc/sysdev/bestcomm/bestcomm_priv.h → include/linux/fsl/bestcomm/bestcomm_priv.h
View File

0
arch/powerpc/sysdev/bestcomm/fec.h → include/linux/fsl/bestcomm/fec.h
View File

0
arch/powerpc/sysdev/bestcomm/gen_bd.h → include/linux/fsl/bestcomm/gen_bd.h
View File

0
arch/powerpc/sysdev/bestcomm/sram.h → include/linux/fsl/bestcomm/sram.h
View File

4
sound/soc/fsl/mpc5200_dma.c
View File

@ -14,8 +14,8 @@
#include <sound/soc.h>
#include <sysdev/bestcomm/bestcomm.h>
#include <sysdev/bestcomm/gen_bd.h>
#include <linux/fsl/bestcomm/bestcomm.h>
#include <linux/fsl/bestcomm/gen_bd.h>
#include <asm/mpc52xx_psc.h>
#include "mpc5200_dma.h"