pinctrl: sh-pfc: Updates for v4.17
- Add DU and VIN pin groups on R-Car D3, - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W, - Add support for the new R-Car M3-N SoC, - Small fixes and cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJamSLtAAoJEEgEtLw/Ve77Qb0QAIaVFrBq4OAfQGTU5wYrJvl2 OMNjt7oPf4LHxqlo979peJ3nxfMZxMCZ1MCIzHEF1hKaOb+PJMrWILt71UJwNnUY TSAgtZUtl6LUxl2F/ZJ7DiqUTKog8m/jfYwgbdva+FlSNd3pWUYCNFX00SGDtonR E/hrx4XYFM+EBuIVrccw/U1u1Cx6FjSEbG7QjBLXlu8ZxBAvHI3V8lyOv0p1jzBt hqNQHsa6O/D2NDypTUCL8Bqe+otZvfnJwQvrNWF7pZBF3m/vaWOROBecZ/QajpPf RftyFEVvtoyeViG7cD0P6h7G0I8kEbzNFODIfLYXjgsNJt88BtotyRTZI/vRG5Ob BSFfkAe4JkRux/7Ry6y/ptMJSZUJcjXo3w8xFXj/DqpA6A+1EyKCypGil6eiGH9q 5kJHpYVDtoQSINWKmOTlu1MQXOo1P+IpYJDgYDOLOHxurRyRQWVW8htRe8zh8WTu 4ikvP8s0kAv7MupISsNUTnwuVD2IdJyaKoMDh6stZOKu0cWzV/+tUOefEZ0xx0HF OeYll9iNrJh0OmIj+wyN770BbaR2q8Gq6W26dxJRAhupGVJw/PrmzDMdqb2FTASp 20Xrjo2ppIZ4AlWgN8Mx5ZPIaVhLS5pmZ2O1CrFQI34a8ZjO3GA72Jx8dUYNh1lS 7Kyn6eCXLbkVbfx9UMUV =mYK2 -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v4.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.17 - Add DU and VIN pin groups on R-Car D3, - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W, - Add support for the new R-Car M3-N SoC, - Small fixes and cleanups.
This commit is contained in:
commit
e024484a86
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@ -15,7 +15,7 @@ Required Properties:
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- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
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- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
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- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
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- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
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- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
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- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
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- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
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- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
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@ -24,6 +24,7 @@ Required Properties:
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- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
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- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
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- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
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- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
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- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
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- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
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- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
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@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
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depends on ARCH_R8A7796
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A77965
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def_bool y
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depends on ARCH_R8A77965
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A77970
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def_bool y
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depends on ARCH_R8A77970
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@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
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obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
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@ -557,6 +557,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
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.data = &r8a7796_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77965
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{
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.compatible = "renesas,pfc-r8a77965",
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.data = &r8a77965_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77970
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{
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.compatible = "renesas,pfc-r8a77970",
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@ -1,7 +1,7 @@
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/*
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* R8A7795 ES1.x processor support - PFC hardware block.
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -2067,6 +2067,22 @@ static const unsigned int du_disp_pins[] = {
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static const unsigned int du_disp_mux[] = {
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DU_DISP_MARK,
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};
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/* - HDMI ------------------------------------------------------------------- */
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static const unsigned int hdmi0_cec_pins[] = {
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/* HDMI0_CEC */
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RCAR_GP_PIN(7, 2),
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};
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static const unsigned int hdmi0_cec_mux[] = {
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HDMI0_CEC_MARK,
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};
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static const unsigned int hdmi1_cec_pins[] = {
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/* HDMI1_CEC */
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RCAR_GP_PIN(7, 3),
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};
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static const unsigned int hdmi1_cec_mux[] = {
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HDMI1_CEC_MARK,
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};
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/* - HSCIF0 ----------------------------------------------------------------- */
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static const unsigned int hscif0_data_pins[] = {
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/* RX, TX */
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@ -3750,6 +3766,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
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SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
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};
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/* - TMU -------------------------------------------------------------------- */
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static const unsigned int tmu_tclk1_a_pins[] = {
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/* TCLK */
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RCAR_GP_PIN(6, 23),
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};
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static const unsigned int tmu_tclk1_a_mux[] = {
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TCLK1_A_MARK,
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};
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static const unsigned int tmu_tclk1_b_pins[] = {
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/* TCLK */
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RCAR_GP_PIN(5, 19),
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};
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static const unsigned int tmu_tclk1_b_mux[] = {
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TCLK1_B_MARK,
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};
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static const unsigned int tmu_tclk2_a_pins[] = {
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/* TCLK */
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RCAR_GP_PIN(6, 19),
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};
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static const unsigned int tmu_tclk2_a_mux[] = {
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TCLK2_A_MARK,
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};
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static const unsigned int tmu_tclk2_b_pins[] = {
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/* TCLK */
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RCAR_GP_PIN(6, 28),
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};
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static const unsigned int tmu_tclk2_b_mux[] = {
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TCLK2_B_MARK,
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};
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/* - USB0 ------------------------------------------------------------------- */
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static const unsigned int usb0_pins[] = {
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/* PWEN, OVC */
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@ -3865,6 +3911,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(du_oddf),
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SH_PFC_PIN_GROUP(du_cde),
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SH_PFC_PIN_GROUP(du_disp),
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SH_PFC_PIN_GROUP(hdmi0_cec),
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SH_PFC_PIN_GROUP(hdmi1_cec),
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SH_PFC_PIN_GROUP(hscif0_data),
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SH_PFC_PIN_GROUP(hscif0_clk),
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SH_PFC_PIN_GROUP(hscif0_ctrl),
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@ -4095,6 +4143,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(ssi9_data_b),
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SH_PFC_PIN_GROUP(ssi9_ctrl_a),
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SH_PFC_PIN_GROUP(ssi9_ctrl_b),
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SH_PFC_PIN_GROUP(tmu_tclk1_a),
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SH_PFC_PIN_GROUP(tmu_tclk1_b),
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SH_PFC_PIN_GROUP(tmu_tclk2_a),
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SH_PFC_PIN_GROUP(tmu_tclk2_b),
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SH_PFC_PIN_GROUP(usb0),
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SH_PFC_PIN_GROUP(usb1),
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SH_PFC_PIN_GROUP(usb2),
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@ -4210,6 +4262,14 @@ static const char * const du_groups[] = {
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"du_disp",
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};
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static const char * const hdmi0_groups[] = {
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"hdmi0_cec",
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};
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static const char * const hdmi1_groups[] = {
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"hdmi1_cec",
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};
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static const char * const hscif0_groups[] = {
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"hscif0_data",
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"hscif0_clk",
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@ -4545,6 +4605,13 @@ static const char * const ssi_groups[] = {
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"ssi9_ctrl_b",
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};
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static const char * const tmu_groups[] = {
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"tmu_tclk1_a",
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"tmu_tclk1_b",
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"tmu_tclk2_a",
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"tmu_tclk2_b",
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};
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static const char * const usb0_groups[] = {
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"usb0",
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};
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@ -4578,6 +4645,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(drif2),
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SH_PFC_FUNCTION(drif3),
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SH_PFC_FUNCTION(du),
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SH_PFC_FUNCTION(hdmi0),
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SH_PFC_FUNCTION(hdmi1),
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SH_PFC_FUNCTION(hscif0),
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SH_PFC_FUNCTION(hscif1),
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SH_PFC_FUNCTION(hscif2),
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@ -4613,6 +4682,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(sdhi2),
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SH_PFC_FUNCTION(sdhi3),
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SH_PFC_FUNCTION(ssi),
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SH_PFC_FUNCTION(tmu),
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SH_PFC_FUNCTION(usb0),
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SH_PFC_FUNCTION(usb1),
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SH_PFC_FUNCTION(usb2),
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@ -1,7 +1,7 @@
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/*
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* R8A7795 ES2.0+ processor support - PFC hardware block.
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*
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* Copyright (C) 2015-2016 Renesas Electronics Corporation
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -472,7 +472,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
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#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
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#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
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#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
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#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
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#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
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#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
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#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
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#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
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@ -1218,7 +1218,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
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PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
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PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
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PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
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PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
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PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
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PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
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PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
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@ -1226,14 +1226,14 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
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PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
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PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
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PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
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PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
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PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
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PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
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PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
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PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
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PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
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PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
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PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
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PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
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PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
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@ -1241,7 +1241,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
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PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
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PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
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PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
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PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
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PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
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PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
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PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
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@ -1250,7 +1250,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
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PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
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PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
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PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
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PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
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PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
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PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
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PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
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@ -1265,7 +1265,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
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PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
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PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
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PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
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PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
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PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
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PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
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PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
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|
@ -1274,7 +1274,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
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PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
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PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
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PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
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PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
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PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
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PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
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PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
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@ -1302,10 +1302,10 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
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/* IPSR15 */
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PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
|
||||
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
|
||||
|
@ -1394,11 +1394,11 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
|
||||
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
|
||||
|
@ -1430,7 +1430,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
|
||||
|
@ -1440,7 +1440,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
|
||||
|
@ -1450,7 +1450,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
|
||||
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
|
||||
|
@ -1462,7 +1462,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
|
||||
PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
|
||||
|
@ -1473,7 +1473,7 @@ static const u16 pinmux_data[] = {
|
|||
/* IPSR18 */
|
||||
PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
|
||||
PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
|
||||
|
@ -1483,7 +1483,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
|
||||
PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
|
||||
|
@ -2128,6 +2128,22 @@ static const unsigned int du_disp_mux[] = {
|
|||
DU_DISP_MARK,
|
||||
};
|
||||
|
||||
/* - HDMI ------------------------------------------------------------------- */
|
||||
static const unsigned int hdmi0_cec_pins[] = {
|
||||
/* HDMI0_CEC */
|
||||
RCAR_GP_PIN(7, 2),
|
||||
};
|
||||
static const unsigned int hdmi0_cec_mux[] = {
|
||||
HDMI0_CEC_MARK,
|
||||
};
|
||||
static const unsigned int hdmi1_cec_pins[] = {
|
||||
/* HDMI1_CEC */
|
||||
RCAR_GP_PIN(7, 3),
|
||||
};
|
||||
static const unsigned int hdmi1_cec_mux[] = {
|
||||
HDMI1_CEC_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int hscif0_data_pins[] = {
|
||||
/* RX, TX */
|
||||
|
@ -3840,6 +3856,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
|
|||
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
|
||||
};
|
||||
|
||||
/* - TMU -------------------------------------------------------------------- */
|
||||
static const unsigned int tmu_tclk1_a_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 23),
|
||||
};
|
||||
static const unsigned int tmu_tclk1_a_mux[] = {
|
||||
TCLK1_A_MARK,
|
||||
};
|
||||
static const unsigned int tmu_tclk1_b_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(5, 19),
|
||||
};
|
||||
static const unsigned int tmu_tclk1_b_mux[] = {
|
||||
TCLK1_B_MARK,
|
||||
};
|
||||
static const unsigned int tmu_tclk2_a_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 19),
|
||||
};
|
||||
static const unsigned int tmu_tclk2_a_mux[] = {
|
||||
TCLK2_A_MARK,
|
||||
};
|
||||
static const unsigned int tmu_tclk2_b_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 28),
|
||||
};
|
||||
static const unsigned int tmu_tclk2_b_mux[] = {
|
||||
TCLK2_B_MARK,
|
||||
};
|
||||
|
||||
/* - USB0 ------------------------------------------------------------------- */
|
||||
static const unsigned int usb0_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
|
@ -3882,6 +3928,400 @@ static const unsigned int usb30_mux[] = {
|
|||
USB30_PWEN_MARK, USB30_OVC_MARK,
|
||||
};
|
||||
|
||||
/* - VIN4 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin4_data8_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
};
|
||||
static const unsigned int vin4_data8_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data8_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
};
|
||||
static const unsigned int vin4_data8_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data10_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
};
|
||||
static const unsigned int vin4_data10_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data10_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
};
|
||||
static const unsigned int vin4_data10_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data12_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
};
|
||||
static const unsigned int vin4_data12_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data12_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
};
|
||||
static const unsigned int vin4_data12_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data16_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin4_data16_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data16_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin4_data16_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data18_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
};
|
||||
static const unsigned int vin4_data18_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data18_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
};
|
||||
static const unsigned int vin4_data18_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data20_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
};
|
||||
static const unsigned int vin4_data20_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data20_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
};
|
||||
static const unsigned int vin4_data20_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data24_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int vin4_data24_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data24_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int vin4_data24_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
|
||||
};
|
||||
static const unsigned int vin4_sync_mux[] = {
|
||||
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
|
||||
};
|
||||
static const unsigned int vin4_field_pins[] = {
|
||||
/* FIELD */
|
||||
RCAR_GP_PIN(1, 16),
|
||||
};
|
||||
static const unsigned int vin4_field_mux[] = {
|
||||
VI4_FIELD_MARK,
|
||||
};
|
||||
static const unsigned int vin4_clkenb_pins[] = {
|
||||
/* CLKENB */
|
||||
RCAR_GP_PIN(1, 19),
|
||||
};
|
||||
static const unsigned int vin4_clkenb_mux[] = {
|
||||
VI4_CLKENB_MARK,
|
||||
};
|
||||
static const unsigned int vin4_clk_pins[] = {
|
||||
/* CLK */
|
||||
RCAR_GP_PIN(1, 27),
|
||||
};
|
||||
static const unsigned int vin4_clk_mux[] = {
|
||||
VI4_CLK_MARK,
|
||||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin5_data8_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int vin5_data8_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data10_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
};
|
||||
static const unsigned int vin5_data10_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data12_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
};
|
||||
static const unsigned int vin5_data12_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data16_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin5_data16_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin5_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
|
||||
};
|
||||
static const unsigned int vin5_sync_mux[] = {
|
||||
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
|
||||
};
|
||||
static const unsigned int vin5_field_pins[] = {
|
||||
RCAR_GP_PIN(1, 11),
|
||||
};
|
||||
static const unsigned int vin5_field_mux[] = {
|
||||
/* FIELD */
|
||||
VI5_FIELD_MARK,
|
||||
};
|
||||
static const unsigned int vin5_clkenb_pins[] = {
|
||||
RCAR_GP_PIN(1, 20),
|
||||
};
|
||||
static const unsigned int vin5_clkenb_mux[] = {
|
||||
/* CLKENB */
|
||||
VI5_CLKENB_MARK,
|
||||
};
|
||||
static const unsigned int vin5_clk_pins[] = {
|
||||
RCAR_GP_PIN(1, 21),
|
||||
};
|
||||
static const unsigned int vin5_clk_mux[] = {
|
||||
/* CLK */
|
||||
VI5_CLK_MARK,
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_a),
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_b),
|
||||
|
@ -3955,6 +4395,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(du_oddf),
|
||||
SH_PFC_PIN_GROUP(du_cde),
|
||||
SH_PFC_PIN_GROUP(du_disp),
|
||||
SH_PFC_PIN_GROUP(hdmi0_cec),
|
||||
SH_PFC_PIN_GROUP(hdmi1_cec),
|
||||
SH_PFC_PIN_GROUP(hscif0_data),
|
||||
SH_PFC_PIN_GROUP(hscif0_clk),
|
||||
SH_PFC_PIN_GROUP(hscif0_ctrl),
|
||||
|
@ -4190,11 +4632,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(ssi9_data_b),
|
||||
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk1_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk1_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_b),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
SH_PFC_PIN_GROUP(usb2),
|
||||
SH_PFC_PIN_GROUP(usb2_ch3),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
SH_PFC_PIN_GROUP(vin4_data8_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data10_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data12_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data16_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data20_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data24_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data8_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data10_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data12_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data16_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data20_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data24_b),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
SH_PFC_PIN_GROUP(vin5_data8),
|
||||
SH_PFC_PIN_GROUP(vin5_data10),
|
||||
SH_PFC_PIN_GROUP(vin5_data12),
|
||||
SH_PFC_PIN_GROUP(vin5_data16),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin5_clk),
|
||||
};
|
||||
|
||||
static const char * const audio_clk_groups[] = {
|
||||
|
@ -4305,6 +4777,14 @@ static const char * const du_groups[] = {
|
|||
"du_disp",
|
||||
};
|
||||
|
||||
static const char * const hdmi0_groups[] = {
|
||||
"hdmi0_cec",
|
||||
};
|
||||
|
||||
static const char * const hdmi1_groups[] = {
|
||||
"hdmi1_cec",
|
||||
};
|
||||
|
||||
static const char * const hscif0_groups[] = {
|
||||
"hscif0_data",
|
||||
"hscif0_clk",
|
||||
|
@ -4639,6 +5119,13 @@ static const char * const ssi_groups[] = {
|
|||
"ssi9_ctrl_b",
|
||||
};
|
||||
|
||||
static const char * const tmu_groups[] = {
|
||||
"tmu_tclk1_a",
|
||||
"tmu_tclk1_b",
|
||||
"tmu_tclk2_a",
|
||||
"tmu_tclk2_b",
|
||||
};
|
||||
|
||||
static const char * const usb0_groups[] = {
|
||||
"usb0",
|
||||
};
|
||||
|
@ -4659,6 +5146,38 @@ static const char * const usb30_groups[] = {
|
|||
"usb30",
|
||||
};
|
||||
|
||||
static const char * const vin4_groups[] = {
|
||||
"vin4_data8_a",
|
||||
"vin4_data10_a",
|
||||
"vin4_data12_a",
|
||||
"vin4_data16_a",
|
||||
"vin4_data18_a",
|
||||
"vin4_data20_a",
|
||||
"vin4_data24_a",
|
||||
"vin4_data8_b",
|
||||
"vin4_data10_b",
|
||||
"vin4_data12_b",
|
||||
"vin4_data16_b",
|
||||
"vin4_data18_b",
|
||||
"vin4_data20_b",
|
||||
"vin4_data24_b",
|
||||
"vin4_sync",
|
||||
"vin4_field",
|
||||
"vin4_clkenb",
|
||||
"vin4_clk",
|
||||
};
|
||||
|
||||
static const char * const vin5_groups[] = {
|
||||
"vin5_data8",
|
||||
"vin5_data10",
|
||||
"vin5_data12",
|
||||
"vin5_data16",
|
||||
"vin5_sync",
|
||||
"vin5_field",
|
||||
"vin5_clkenb",
|
||||
"vin5_clk",
|
||||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb),
|
||||
|
@ -4672,6 +5191,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(hdmi0),
|
||||
SH_PFC_FUNCTION(hdmi1),
|
||||
SH_PFC_FUNCTION(hscif0),
|
||||
SH_PFC_FUNCTION(hscif1),
|
||||
SH_PFC_FUNCTION(hscif2),
|
||||
|
@ -4705,11 +5226,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(sdhi2),
|
||||
SH_PFC_FUNCTION(sdhi3),
|
||||
SH_PFC_FUNCTION(ssi),
|
||||
SH_PFC_FUNCTION(tmu),
|
||||
SH_PFC_FUNCTION(usb0),
|
||||
SH_PFC_FUNCTION(usb1),
|
||||
SH_PFC_FUNCTION(usb2),
|
||||
SH_PFC_FUNCTION(usb2_ch3),
|
||||
SH_PFC_FUNCTION(usb30),
|
||||
SH_PFC_FUNCTION(vin4),
|
||||
SH_PFC_FUNCTION(vin5),
|
||||
};
|
||||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* R8A7796 processor support - PFC hardware block.
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
|
||||
*
|
||||
|
@ -477,7 +477,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
|
|||
#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
|
||||
#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
|
||||
#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
|
||||
#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
|
||||
#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
|
||||
#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
|
||||
#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
|
||||
|
@ -502,7 +502,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
|
|||
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
|
||||
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
|
||||
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
|
||||
#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
|
||||
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
|
||||
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
|
||||
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
|
||||
|
@ -1016,35 +1016,35 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
|
||||
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
|
||||
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
|
||||
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
|
||||
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
|
||||
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
|
||||
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
|
||||
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
|
||||
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
|
||||
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
|
||||
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
|
||||
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
|
||||
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
|
||||
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
|
||||
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
|
||||
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
|
||||
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
|
||||
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
|
||||
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
|
||||
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
|
||||
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
|
||||
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
|
||||
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
|
||||
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
|
||||
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
|
||||
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
|
||||
|
||||
|
@ -1110,16 +1110,20 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
|
||||
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
|
||||
|
@ -1218,7 +1222,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
|
||||
|
@ -1226,14 +1230,14 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
|
||||
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
|
||||
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
|
||||
|
@ -1241,7 +1245,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
|
||||
|
@ -1250,7 +1254,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
|
||||
PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
|
||||
PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
|
||||
PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
|
||||
PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
|
||||
|
@ -1263,9 +1267,9 @@ static const u16 pinmux_data[] = {
|
|||
/* IPSR14 */
|
||||
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
|
||||
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
|
||||
|
@ -1274,7 +1278,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
|
||||
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
|
||||
|
@ -1302,10 +1306,10 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
|
||||
|
||||
/* IPSR15 */
|
||||
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
|
||||
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
|
||||
|
@ -1391,11 +1395,11 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
|
||||
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
|
||||
|
@ -1427,7 +1431,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
|
||||
PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
|
||||
|
@ -1437,7 +1441,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
|
||||
PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
|
||||
|
@ -1447,7 +1451,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
|
||||
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
|
||||
|
@ -1459,7 +1463,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
|
||||
PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
|
||||
|
@ -1470,7 +1474,7 @@ static const u16 pinmux_data[] = {
|
|||
/* IPSR18 */
|
||||
PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
|
||||
PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
|
||||
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
|
||||
|
@ -1480,7 +1484,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
|
||||
PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
|
||||
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
|
||||
|
@ -2129,6 +2133,15 @@ static const unsigned int du_disp_mux[] = {
|
|||
DU_DISP_MARK,
|
||||
};
|
||||
|
||||
/* - HDMI ------------------------------------------------------------------- */
|
||||
static const unsigned int hdmi0_cec_pins[] = {
|
||||
/* HDMI0_CEC */
|
||||
RCAR_GP_PIN(7, 2),
|
||||
};
|
||||
static const unsigned int hdmi0_cec_mux[] = {
|
||||
HDMI0_CEC_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int hscif0_data_pins[] = {
|
||||
/* RX, TX */
|
||||
|
@ -3827,6 +3840,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
|
|||
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
|
||||
};
|
||||
|
||||
/* - TMU -------------------------------------------------------------------- */
|
||||
static const unsigned int tmu_tclk1_a_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 23),
|
||||
};
|
||||
static const unsigned int tmu_tclk1_a_mux[] = {
|
||||
TCLK1_A_MARK,
|
||||
};
|
||||
static const unsigned int tmu_tclk1_b_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(5, 19),
|
||||
};
|
||||
static const unsigned int tmu_tclk1_b_mux[] = {
|
||||
TCLK1_B_MARK,
|
||||
};
|
||||
static const unsigned int tmu_tclk2_a_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 19),
|
||||
};
|
||||
static const unsigned int tmu_tclk2_a_mux[] = {
|
||||
TCLK2_A_MARK,
|
||||
};
|
||||
static const unsigned int tmu_tclk2_b_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 28),
|
||||
};
|
||||
static const unsigned int tmu_tclk2_b_mux[] = {
|
||||
TCLK2_B_MARK,
|
||||
};
|
||||
|
||||
/* - USB0 ------------------------------------------------------------------- */
|
||||
static const unsigned int usb0_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
|
@ -3853,6 +3896,400 @@ static const unsigned int usb30_mux[] = {
|
|||
USB30_PWEN_MARK, USB30_OVC_MARK,
|
||||
};
|
||||
|
||||
/* - VIN4 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin4_data8_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
};
|
||||
static const unsigned int vin4_data8_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data8_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
};
|
||||
static const unsigned int vin4_data8_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data10_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
};
|
||||
static const unsigned int vin4_data10_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data10_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
};
|
||||
static const unsigned int vin4_data10_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data12_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
};
|
||||
static const unsigned int vin4_data12_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data12_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
};
|
||||
static const unsigned int vin4_data12_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data16_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin4_data16_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data16_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin4_data16_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data18_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
};
|
||||
static const unsigned int vin4_data18_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data18_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
};
|
||||
static const unsigned int vin4_data18_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data20_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
};
|
||||
static const unsigned int vin4_data20_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data20_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
};
|
||||
static const unsigned int vin4_data20_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data24_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int vin4_data24_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data24_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int vin4_data24_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
|
||||
};
|
||||
static const unsigned int vin4_sync_mux[] = {
|
||||
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
|
||||
};
|
||||
static const unsigned int vin4_field_pins[] = {
|
||||
/* FIELD */
|
||||
RCAR_GP_PIN(1, 16),
|
||||
};
|
||||
static const unsigned int vin4_field_mux[] = {
|
||||
VI4_FIELD_MARK,
|
||||
};
|
||||
static const unsigned int vin4_clkenb_pins[] = {
|
||||
/* CLKENB */
|
||||
RCAR_GP_PIN(1, 19),
|
||||
};
|
||||
static const unsigned int vin4_clkenb_mux[] = {
|
||||
VI4_CLKENB_MARK,
|
||||
};
|
||||
static const unsigned int vin4_clk_pins[] = {
|
||||
/* CLK */
|
||||
RCAR_GP_PIN(1, 27),
|
||||
};
|
||||
static const unsigned int vin4_clk_mux[] = {
|
||||
VI4_CLK_MARK,
|
||||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin5_data8_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int vin5_data8_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data10_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
};
|
||||
static const unsigned int vin5_data10_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data12_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
};
|
||||
static const unsigned int vin5_data12_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data16_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin5_data16_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin5_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
|
||||
};
|
||||
static const unsigned int vin5_sync_mux[] = {
|
||||
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
|
||||
};
|
||||
static const unsigned int vin5_field_pins[] = {
|
||||
RCAR_GP_PIN(1, 11),
|
||||
};
|
||||
static const unsigned int vin5_field_mux[] = {
|
||||
/* FIELD */
|
||||
VI5_FIELD_MARK,
|
||||
};
|
||||
static const unsigned int vin5_clkenb_pins[] = {
|
||||
RCAR_GP_PIN(1, 20),
|
||||
};
|
||||
static const unsigned int vin5_clkenb_mux[] = {
|
||||
/* CLKENB */
|
||||
VI5_CLKENB_MARK,
|
||||
};
|
||||
static const unsigned int vin5_clk_pins[] = {
|
||||
RCAR_GP_PIN(1, 21),
|
||||
};
|
||||
static const unsigned int vin5_clk_mux[] = {
|
||||
/* CLK */
|
||||
VI5_CLK_MARK,
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_a),
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_b),
|
||||
|
@ -3926,6 +4363,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(du_oddf),
|
||||
SH_PFC_PIN_GROUP(du_cde),
|
||||
SH_PFC_PIN_GROUP(du_disp),
|
||||
SH_PFC_PIN_GROUP(hdmi0_cec),
|
||||
SH_PFC_PIN_GROUP(hscif0_data),
|
||||
SH_PFC_PIN_GROUP(hscif0_clk),
|
||||
SH_PFC_PIN_GROUP(hscif0_ctrl),
|
||||
|
@ -4159,9 +4597,39 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(ssi9_data_b),
|
||||
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk1_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk1_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_b),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
SH_PFC_PIN_GROUP(vin4_data8_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data10_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data12_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data16_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data20_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data24_a),
|
||||
SH_PFC_PIN_GROUP(vin4_data8_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data10_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data12_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data16_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data20_b),
|
||||
SH_PFC_PIN_GROUP(vin4_data24_b),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
SH_PFC_PIN_GROUP(vin5_data8),
|
||||
SH_PFC_PIN_GROUP(vin5_data10),
|
||||
SH_PFC_PIN_GROUP(vin5_data12),
|
||||
SH_PFC_PIN_GROUP(vin5_data16),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin5_clk),
|
||||
};
|
||||
|
||||
static const char * const audio_clk_groups[] = {
|
||||
|
@ -4272,6 +4740,10 @@ static const char * const du_groups[] = {
|
|||
"du_disp",
|
||||
};
|
||||
|
||||
static const char * const hdmi0_groups[] = {
|
||||
"hdmi0_cec",
|
||||
};
|
||||
|
||||
static const char * const hscif0_groups[] = {
|
||||
"hscif0_data",
|
||||
"hscif0_clk",
|
||||
|
@ -4601,6 +5073,13 @@ static const char * const ssi_groups[] = {
|
|||
"ssi9_ctrl_b",
|
||||
};
|
||||
|
||||
static const char * const tmu_groups[] = {
|
||||
"tmu_tclk1_a",
|
||||
"tmu_tclk1_b",
|
||||
"tmu_tclk2_a",
|
||||
"tmu_tclk2_b",
|
||||
};
|
||||
|
||||
static const char * const usb0_groups[] = {
|
||||
"usb0",
|
||||
};
|
||||
|
@ -4613,6 +5092,38 @@ static const char * const usb30_groups[] = {
|
|||
"usb30",
|
||||
};
|
||||
|
||||
static const char * const vin4_groups[] = {
|
||||
"vin4_data8_a",
|
||||
"vin4_data10_a",
|
||||
"vin4_data12_a",
|
||||
"vin4_data16_a",
|
||||
"vin4_data18_a",
|
||||
"vin4_data20_a",
|
||||
"vin4_data24_a",
|
||||
"vin4_data8_b",
|
||||
"vin4_data10_b",
|
||||
"vin4_data12_b",
|
||||
"vin4_data16_b",
|
||||
"vin4_data18_b",
|
||||
"vin4_data20_b",
|
||||
"vin4_data24_b",
|
||||
"vin4_sync",
|
||||
"vin4_field",
|
||||
"vin4_clkenb",
|
||||
"vin4_clk",
|
||||
};
|
||||
|
||||
static const char * const vin5_groups[] = {
|
||||
"vin5_data8",
|
||||
"vin5_data10",
|
||||
"vin5_data12",
|
||||
"vin5_data16",
|
||||
"vin5_sync",
|
||||
"vin5_field",
|
||||
"vin5_clkenb",
|
||||
"vin5_clk",
|
||||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb),
|
||||
|
@ -4626,6 +5137,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(hdmi0),
|
||||
SH_PFC_FUNCTION(hscif0),
|
||||
SH_PFC_FUNCTION(hscif1),
|
||||
SH_PFC_FUNCTION(hscif2),
|
||||
|
@ -4658,9 +5170,12 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(sdhi2),
|
||||
SH_PFC_FUNCTION(sdhi3),
|
||||
SH_PFC_FUNCTION(ssi),
|
||||
SH_PFC_FUNCTION(tmu),
|
||||
SH_PFC_FUNCTION(usb0),
|
||||
SH_PFC_FUNCTION(usb1),
|
||||
SH_PFC_FUNCTION(usb30),
|
||||
SH_PFC_FUNCTION(vin4),
|
||||
SH_PFC_FUNCTION(vin5),
|
||||
};
|
||||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
|
|
3193
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
Normal file
3193
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -1114,6 +1114,87 @@ static const unsigned int canfd1_data_mux[] = {
|
|||
CANFD1_TX_MARK, CANFD1_RX_MARK,
|
||||
};
|
||||
|
||||
/* - DU --------------------------------------------------------------------- */
|
||||
static const unsigned int du_rgb666_pins[] = {
|
||||
/* R[7:2], G[7:2], B[7:2] */
|
||||
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
|
||||
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
|
||||
};
|
||||
static const unsigned int du_rgb666_mux[] = {
|
||||
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
|
||||
DU_DR3_MARK, DU_DR2_MARK,
|
||||
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
|
||||
DU_DG3_MARK, DU_DG2_MARK,
|
||||
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
|
||||
DU_DB3_MARK, DU_DB2_MARK,
|
||||
};
|
||||
static const unsigned int du_rgb888_pins[] = {
|
||||
/* R[7:0], G[7:0], B[7:0] */
|
||||
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
|
||||
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
|
||||
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
|
||||
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
|
||||
};
|
||||
static const unsigned int du_rgb888_mux[] = {
|
||||
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
|
||||
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
|
||||
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
|
||||
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
|
||||
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
|
||||
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
|
||||
};
|
||||
static const unsigned int du_clk_in_1_pins[] = {
|
||||
/* CLKIN */
|
||||
RCAR_GP_PIN(1, 28),
|
||||
};
|
||||
static const unsigned int du_clk_in_1_mux[] = {
|
||||
DU_DOTCLKIN1_MARK
|
||||
};
|
||||
static const unsigned int du_clk_out_0_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(1, 24),
|
||||
};
|
||||
static const unsigned int du_clk_out_0_mux[] = {
|
||||
DU_DOTCLKOUT0_MARK
|
||||
};
|
||||
static const unsigned int du_sync_pins[] = {
|
||||
/* VSYNC, HSYNC */
|
||||
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
|
||||
};
|
||||
static const unsigned int du_sync_mux[] = {
|
||||
DU_VSYNC_MARK, DU_HSYNC_MARK
|
||||
};
|
||||
static const unsigned int du_disp_cde_pins[] = {
|
||||
/* DISP_CDE */
|
||||
RCAR_GP_PIN(1, 28),
|
||||
};
|
||||
static const unsigned int du_disp_cde_mux[] = {
|
||||
DU_DISP_CDE_MARK,
|
||||
};
|
||||
static const unsigned int du_cde_pins[] = {
|
||||
/* CDE */
|
||||
RCAR_GP_PIN(1, 29),
|
||||
};
|
||||
static const unsigned int du_cde_mux[] = {
|
||||
DU_CDE_MARK,
|
||||
};
|
||||
static const unsigned int du_disp_pins[] = {
|
||||
/* DISP */
|
||||
RCAR_GP_PIN(1, 27),
|
||||
};
|
||||
static const unsigned int du_disp_mux[] = {
|
||||
DU_DISP_MARK,
|
||||
};
|
||||
|
||||
/* - I2C -------------------------------------------------------------------- */
|
||||
static const unsigned int i2c0_pins[] = {
|
||||
/* SCL, SDA */
|
||||
|
@ -1545,6 +1626,172 @@ static const unsigned int usb0_mux[] = {
|
|||
USB0_PWEN_MARK, USB0_OVC_MARK,
|
||||
};
|
||||
|
||||
/* - VIN4 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin4_data8_pins[] = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
};
|
||||
static const unsigned int vin4_data8_mux[] = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data10_pins[] = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
};
|
||||
static const unsigned int vin4_data10_mux[] = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data12_pins[] = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
|
||||
};
|
||||
static const unsigned int vin4_data12_mux[] = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data16_pins[] = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
|
||||
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
|
||||
};
|
||||
static const unsigned int vin4_data16_mux[] = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data18_pins[] = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
|
||||
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
};
|
||||
static const unsigned int vin4_data18_mux[] = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data20_pins[] = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
|
||||
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
};
|
||||
static const unsigned int vin4_data20_mux[] = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data24_pins[] = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
|
||||
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
|
||||
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
|
||||
};
|
||||
static const unsigned int vin4_data24_mux[] = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
|
||||
};
|
||||
static const unsigned int vin4_sync_mux[] = {
|
||||
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
|
||||
};
|
||||
static const unsigned int vin4_field_pins[] = {
|
||||
/* FIELD */
|
||||
RCAR_GP_PIN(2, 27),
|
||||
};
|
||||
static const unsigned int vin4_field_mux[] = {
|
||||
VI4_FIELD_MARK,
|
||||
};
|
||||
static const unsigned int vin4_clkenb_pins[] = {
|
||||
/* CLKENB */
|
||||
RCAR_GP_PIN(2, 28),
|
||||
};
|
||||
static const unsigned int vin4_clkenb_mux[] = {
|
||||
VI4_CLKENB_MARK,
|
||||
};
|
||||
static const unsigned int vin4_clk_pins[] = {
|
||||
/* CLK */
|
||||
RCAR_GP_PIN(2, 0),
|
||||
};
|
||||
static const unsigned int vin4_clk_mux[] = {
|
||||
VI4_CLK_MARK,
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(audio_clk_a),
|
||||
SH_PFC_PIN_GROUP(audio_clk_b),
|
||||
|
@ -1568,6 +1815,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(can_clk),
|
||||
SH_PFC_PIN_GROUP(canfd0_data),
|
||||
SH_PFC_PIN_GROUP(canfd1_data),
|
||||
SH_PFC_PIN_GROUP(du_rgb666),
|
||||
SH_PFC_PIN_GROUP(du_rgb888),
|
||||
SH_PFC_PIN_GROUP(du_clk_in_1),
|
||||
SH_PFC_PIN_GROUP(du_clk_out_0),
|
||||
SH_PFC_PIN_GROUP(du_sync),
|
||||
SH_PFC_PIN_GROUP(du_disp_cde),
|
||||
SH_PFC_PIN_GROUP(du_cde),
|
||||
SH_PFC_PIN_GROUP(du_disp),
|
||||
SH_PFC_PIN_GROUP(i2c0),
|
||||
SH_PFC_PIN_GROUP(i2c1),
|
||||
SH_PFC_PIN_GROUP(i2c2_a),
|
||||
|
@ -1622,6 +1877,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(ssi4_data_b),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(vin4_data8),
|
||||
SH_PFC_PIN_GROUP(vin4_data10),
|
||||
SH_PFC_PIN_GROUP(vin4_data12),
|
||||
SH_PFC_PIN_GROUP(vin4_data16),
|
||||
SH_PFC_PIN_GROUP(vin4_data18),
|
||||
SH_PFC_PIN_GROUP(vin4_data20),
|
||||
SH_PFC_PIN_GROUP(vin4_data24),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
};
|
||||
|
||||
static const char * const audio_clk_groups[] = {
|
||||
|
@ -1664,6 +1930,17 @@ static const char * const canfd1_groups[] = {
|
|||
"canfd1_data",
|
||||
};
|
||||
|
||||
static const char * const du_groups[] = {
|
||||
"du_rgb666",
|
||||
"du_rgb888",
|
||||
"du_clk_in_1",
|
||||
"du_clk_out_0",
|
||||
"du_sync",
|
||||
"du_disp_cde",
|
||||
"du_cde",
|
||||
"du_disp",
|
||||
};
|
||||
|
||||
static const char * const i2c0_groups[] = {
|
||||
"i2c0",
|
||||
};
|
||||
|
@ -1771,6 +2048,20 @@ static const char * const usb0_groups[] = {
|
|||
"usb0",
|
||||
};
|
||||
|
||||
static const char * const vin4_groups[] = {
|
||||
"vin4_data8",
|
||||
"vin4_data10",
|
||||
"vin4_data12",
|
||||
"vin4_data16",
|
||||
"vin4_data18",
|
||||
"vin4_data20",
|
||||
"vin4_data24",
|
||||
"vin4_sync",
|
||||
"vin4_field",
|
||||
"vin4_clkenb",
|
||||
"vin4_clk",
|
||||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb0),
|
||||
|
@ -1779,6 +2070,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(can_clk),
|
||||
SH_PFC_FUNCTION(canfd0),
|
||||
SH_PFC_FUNCTION(canfd1),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(i2c0),
|
||||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
|
@ -1797,6 +2089,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(scif_clk),
|
||||
SH_PFC_FUNCTION(ssi),
|
||||
SH_PFC_FUNCTION(usb0),
|
||||
SH_PFC_FUNCTION(vin4),
|
||||
};
|
||||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
|
|
|
@ -75,7 +75,7 @@ static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
||||
unsigned offset)
|
||||
{
|
||||
seq_printf(s, "%s", DRV_NAME);
|
||||
seq_puts(s, DRV_NAME);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
|
|
@ -283,6 +283,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
|||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
|
||||
|
|
Loading…
Reference in a new issue