drivers: net: xgene: Fix hardware checksum setting
This patch fixes the hardware checksum settings by properly program the classifier. Otherwise, packet may be received with checksum error on X-Gene1 SoC. Signed-off-by: Quan Nguyen <qnguyen@apm.com> Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -623,6 +623,7 @@ static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
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xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
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cb |= CFG_CLE_BYPASS_EN0;
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CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
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CFG_CLE_IP_HDR_LEN_SET(&cb, 0);
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xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
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xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
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@ -163,6 +163,7 @@ enum xgene_enet_rm {
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#define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)
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#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
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#define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
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#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
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#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
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#define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4)
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