usb: dwc2: gadget: EP 0 specific DDMA programming
Add dwc2_gadget_set_ep0_desc_chain() function to switch between EP0 DDMA chains depend on the stage of control transfer. Include EP0 DDMA chain selection during ep_queue called from dwc2_hsotg_enqueue_setup() for setup stage. Selecting and filling DDMA chain for status phase as well - add calls of dwc2_gadget_set_ep0_desc_chain() and dwc2_gadget_config_nonisoc_xfer_ddma() functions. Signed-off-by: Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>hifive-unleashed-5.1
Vahram Aharonyan
Felipe Balbi
parent
8ad07335e8
commit
e02f9aa611
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@ -627,6 +627,114 @@ static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
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return maxsize;
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}
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/*
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* dwc2_gadget_get_desc_params - get DMA descriptor parameters.
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* @hs_ep: The endpoint
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* @mask: RX/TX bytes mask to be defined
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*
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* Returns maximum data payload for one descriptor after analyzing endpoint
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* characteristics.
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* DMA descriptor transfer bytes limit depends on EP type:
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* Control out - MPS,
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* Isochronous - descriptor rx/tx bytes bitfield limit,
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* Control In/Bulk/Interrupt - multiple of mps. This will allow to not
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* have concatenations from various descriptors within one packet.
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*
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* Selects corresponding mask for RX/TX bytes as well.
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*/
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static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
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{
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u32 mps = hs_ep->ep.maxpacket;
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int dir_in = hs_ep->dir_in;
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u32 desc_size = 0;
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if (!hs_ep->index && !dir_in) {
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desc_size = mps;
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*mask = DEV_DMA_NBYTES_MASK;
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} else if (hs_ep->isochronous) {
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if (dir_in) {
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desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
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*mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
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} else {
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desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
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*mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
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}
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} else {
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desc_size = DEV_DMA_NBYTES_LIMIT;
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*mask = DEV_DMA_NBYTES_MASK;
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/* Round down desc_size to be mps multiple */
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desc_size -= desc_size % mps;
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}
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return desc_size;
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}
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/*
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* dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
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* @hs_ep: The endpoint
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* @dma_buff: DMA address to use
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* @len: Length of the transfer
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*
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* This function will iterate over descriptor chain and fill its entries
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* with corresponding information based on transfer data.
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*/
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static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
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dma_addr_t dma_buff,
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unsigned int len)
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{
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struct dwc2_hsotg *hsotg = hs_ep->parent;
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int dir_in = hs_ep->dir_in;
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struct dwc2_dma_desc *desc = hs_ep->desc_list;
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u32 mps = hs_ep->ep.maxpacket;
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u32 maxsize = 0;
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u32 offset = 0;
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u32 mask = 0;
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int i;
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maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
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hs_ep->desc_count = (len / maxsize) +
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((len % maxsize) ? 1 : 0);
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if (len == 0)
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hs_ep->desc_count = 1;
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for (i = 0; i < hs_ep->desc_count; ++i) {
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desc->status = 0;
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desc->status |= (DEV_DMA_BUFF_STS_HBUSY
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<< DEV_DMA_BUFF_STS_SHIFT);
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if (len > maxsize) {
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if (!hs_ep->index && !dir_in)
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desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
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desc->status |= (maxsize <<
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DEV_DMA_NBYTES_SHIFT & mask);
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desc->buf = dma_buff + offset;
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len -= maxsize;
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offset += maxsize;
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} else {
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desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
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if (dir_in)
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desc->status |= (len % mps) ? DEV_DMA_SHORT :
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((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
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if (len > maxsize)
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dev_err(hsotg->dev, "wrong len %d\n", len);
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desc->status |=
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len << DEV_DMA_NBYTES_SHIFT & mask;
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desc->buf = dma_buff + offset;
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}
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desc->status &= ~DEV_DMA_BUFF_STS_MASK;
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desc->status |= (DEV_DMA_BUFF_STS_HREADY
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<< DEV_DMA_BUFF_STS_SHIFT);
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desc++;
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}
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}
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/**
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* dwc2_hsotg_start_req - start a USB request from an endpoint's queue
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* @hsotg: The controller state.
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@ -926,6 +1034,41 @@ static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
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return false;
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}
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/*
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* dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
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* @hsotg: The driver state
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* @hs_ep: the ep descriptor chain is for
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*
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* Called to update EP0 structure's pointers depend on stage of
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* control transfer.
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*/
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static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
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struct dwc2_hsotg_ep *hs_ep)
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{
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switch (hsotg->ep0_state) {
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case DWC2_EP0_SETUP:
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case DWC2_EP0_STATUS_OUT:
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hs_ep->desc_list = hsotg->setup_desc[0];
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hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
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break;
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case DWC2_EP0_DATA_IN:
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case DWC2_EP0_STATUS_IN:
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hs_ep->desc_list = hsotg->ctrl_in_desc;
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hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
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break;
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case DWC2_EP0_DATA_OUT:
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hs_ep->desc_list = hsotg->ctrl_out_desc;
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hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
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break;
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default:
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dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
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hsotg->ep0_state);
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return -EINVAL;
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}
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return 0;
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}
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static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
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gfp_t gfp_flags)
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{
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@ -961,6 +1104,12 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
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if (ret)
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return ret;
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}
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/* If using descriptor DMA configure EP0 descriptor chain pointers */
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if (using_desc_dma(hs) && !hs_ep->index) {
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ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
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if (ret)
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return ret;
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}
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first = list_empty(&hs_ep->queue);
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list_add_tail(&hs_req->queue, &hs_ep->queue);
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@ -1529,14 +1678,21 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
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if (hs_ep->dir_in)
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dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
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index);
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index);
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else
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dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
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index);
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index);
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if (using_desc_dma(hsotg)) {
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/* Not specific buffer needed for ep0 ZLP */
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dma_addr_t dma = hs_ep->desc_list_dma;
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dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
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DXEPTSIZ_XFERSIZE(0), hsotg->regs +
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epsiz_reg);
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dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
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dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
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} else {
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dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
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DXEPTSIZ_XFERSIZE(0), hsotg->regs +
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epsiz_reg);
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}
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ctrl = dwc2_readl(hsotg->regs + epctl_reg);
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ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
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