sh: use ctrl_in/out for on chip pci access
This patch makes sure ctrl_inN/outN are used instead of inN/outN for on chip pci registers. Without this patch addresses may be adjusted using the value in generic_io_base. This patch makes it possible to set generic_io_base and have pci without reading and writing all over the place. Signed-off-by: Magnus Damm <damm@igel.co.jp> Acked-by: Katsuya MATSUBARA <matsu@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -18,7 +18,7 @@ int pci_fixup_pcic(void)
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{
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unsigned long bcr1, mcr;
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bcr1 = inl(SH7751_BCR1);
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bcr1 = ctrl_inl(SH7751_BCR1);
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bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
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pci_write_reg(bcr1, SH4_PCIBCR1);
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@ -28,7 +28,7 @@ int pci_fixup_pcic(void)
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pci_write_reg(0xfb900047, SH7751_PCICONF1);
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pci_write_reg(0xab000001, SH7751_PCICONF4);
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mcr = inl(SH7751_MCR);
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mcr = ctrl_inl(SH7751_MCR);
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mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
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pci_write_reg(mcr, SH4_PCIMCR);
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@ -19,7 +19,7 @@ int pci_fixup_pcic(void)
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{
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unsigned long bcr1, mcr;
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bcr1 = inl(SH7751_BCR1);
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bcr1 = ctrl_inl(SH7751_BCR1);
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bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
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pci_write_reg(bcr1, SH4_PCIBCR1);
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@ -30,7 +30,7 @@ int pci_fixup_pcic(void)
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pci_write_reg(0xfb900047, SH7751_PCICONF1);
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pci_write_reg(0xab000001, SH7751_PCICONF4);
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mcr = inl(SH7751_MCR);
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mcr = ctrl_inl(SH7751_MCR);
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mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
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pci_write_reg(mcr, SH4_PCIMCR);
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@ -83,9 +83,9 @@ static int gapspci_read(struct pci_bus *bus, unsigned int devfn, int where, int
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1: *val = inb(GAPSPCI_BBA_CONFIG+where); break;
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case 2: *val = inw(GAPSPCI_BBA_CONFIG+where); break;
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case 4: *val = inl(GAPSPCI_BBA_CONFIG+where); break;
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case 1: *val = ctrl_inb(GAPSPCI_BBA_CONFIG+where); break;
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case 2: *val = ctrl_inw(GAPSPCI_BBA_CONFIG+where); break;
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case 4: *val = ctrl_inl(GAPSPCI_BBA_CONFIG+where); break;
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}
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return PCIBIOS_SUCCESSFUL;
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@ -97,9 +97,9 @@ static int gapspci_write(struct pci_bus *bus, unsigned int devfn, int where, int
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1: outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break;
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case 2: outw((u16)val, GAPSPCI_BBA_CONFIG+where); break;
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case 4: outl((u32)val, GAPSPCI_BBA_CONFIG+where); break;
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case 1: ctrl_outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break;
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case 2: ctrl_outw((u16)val, GAPSPCI_BBA_CONFIG+where); break;
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case 4: ctrl_outl((u32)val, GAPSPCI_BBA_CONFIG+where); break;
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}
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return PCIBIOS_SUCCESSFUL;
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@ -127,36 +127,36 @@ int __init gapspci_init(void)
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*/
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for (i=0; i<16; i++)
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idbuf[i] = inb(GAPSPCI_REGS+i);
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idbuf[i] = ctrl_inb(GAPSPCI_REGS+i);
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if (strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
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return -ENODEV;
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outl(0x5a14a501, GAPSPCI_REGS+0x18);
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ctrl_outl(0x5a14a501, GAPSPCI_REGS+0x18);
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for (i=0; i<1000000; i++)
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;
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if (inl(GAPSPCI_REGS+0x18) != 1)
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if (ctrl_inl(GAPSPCI_REGS+0x18) != 1)
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return -EINVAL;
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outl(0x01000000, GAPSPCI_REGS+0x20);
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outl(0x01000000, GAPSPCI_REGS+0x24);
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ctrl_outl(0x01000000, GAPSPCI_REGS+0x20);
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ctrl_outl(0x01000000, GAPSPCI_REGS+0x24);
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outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
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outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
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ctrl_outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
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ctrl_outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
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outl(1, GAPSPCI_REGS+0x14);
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outl(1, GAPSPCI_REGS+0x34);
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ctrl_outl(1, GAPSPCI_REGS+0x14);
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ctrl_outl(1, GAPSPCI_REGS+0x34);
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/* Setting Broadband Adapter */
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outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
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outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
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outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
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outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
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outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
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outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
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outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
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ctrl_outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
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ctrl_outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
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ctrl_outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
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ctrl_outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
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ctrl_outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
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ctrl_outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
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ctrl_outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
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return 0;
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}
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@ -172,11 +172,11 @@ struct sh4_pci_address_map {
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static inline void pci_write_reg(unsigned long val, unsigned long reg)
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{
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outl(val, PCI_REG(reg));
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ctrl_outl(val, PCI_REG(reg));
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}
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static inline unsigned long pci_read_reg(unsigned long reg)
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{
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return inl(PCI_REG(reg));
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return ctrl_inl(PCI_REG(reg));
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}
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#endif /* __PCI_SH4_H */
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@ -58,7 +58,7 @@ static int __init __area_sdram_check(unsigned int area)
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{
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u32 word;
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word = inl(SH7751_BCR1);
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word = ctrl_inl(SH7751_BCR1);
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/* check BCR for SDRAM in area */
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if (((word >> area) & 1) == 0) {
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printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
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@ -67,7 +67,7 @@ static int __init __area_sdram_check(unsigned int area)
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}
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pci_write_reg(word, SH4_PCIBCR1);
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word = (u16)inw(SH7751_BCR2);
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word = (u16)ctrl_inw(SH7751_BCR2);
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/* check BCR2 for 32bit SDRAM interface*/
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if (((word >> (area << 1)) & 0x3) != 0x3) {
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printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
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@ -85,9 +85,9 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
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u32 word;
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/* Set the BCR's to enable PCI access */
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reg = inl(SH7751_BCR1);
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reg = ctrl_inl(SH7751_BCR1);
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reg |= 0x80000;
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outl(reg, SH7751_BCR1);
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ctrl_outl(reg, SH7751_BCR1);
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/* Turn the clocks back on (not done in reset)*/
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pci_write_reg(0, SH4_PCICLKR);
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@ -179,13 +179,13 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
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return 0;
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/* configure the wait control registers */
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word = inl(SH7751_WCR1);
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word = ctrl_inl(SH7751_WCR1);
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pci_write_reg(word, SH4_PCIWCR1);
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word = inl(SH7751_WCR2);
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word = ctrl_inl(SH7751_WCR2);
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pci_write_reg(word, SH4_PCIWCR2);
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word = inl(SH7751_WCR3);
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word = ctrl_inl(SH7751_WCR3);
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pci_write_reg(word, SH4_PCIWCR3);
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word = inl(SH7751_MCR);
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word = ctrl_inl(SH7751_MCR);
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pci_write_reg(word, SH4_PCIMCR);
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/* NOTE: I'm ignoring the PCI error IRQs for now..
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@ -52,7 +52,7 @@ static int __init sh7780_pci_init(void)
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pr_debug("PCI: Starting intialization.\n");
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outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
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ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
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/* check for SH7780/SH7780R hardware */
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id = pci_read_reg(SH7780_PCIVID);
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