tty: serial: fsl_lpuart: enable dma mode for imx8qxp
imx8qxp lpuart support eDMA for dma mode, support EOP (end-of-packet) feature. But eDMA cannot detect the correct DADDR for current major loop in cyclic mode, so it doesn't support cyclic mode. The patch is to enable lpuart prep slave sg dma mode for imx8qxp. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>5.4-rM2-2.2.x-imx-squashed
Fugang Duan
Dong Aisheng
parent
a2d1059cb9
commit
e085dff6cb
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@ -131,6 +131,7 @@
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#define UARTBAUD_M10 0x20000000
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#define UARTBAUD_TDMAE 0x00800000
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#define UARTBAUD_RDMAE 0x00200000
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#define UARTBAUD_RIDMAE 0x00100000
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#define UARTBAUD_MATCFG 0x00400000
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#define UARTBAUD_BOTHEDGE 0x00020000
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#define UARTBAUD_RESYNCDIS 0x00010000
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@ -179,7 +180,7 @@
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#define UARTCTRL_SBK 0x00010000
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#define UARTCTRL_MA1IE 0x00008000
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#define UARTCTRL_MA2IE 0x00004000
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#define UARTCTRL_IDLECFG 0x00000100
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#define UARTCTRL_IDLECFG_OFF 0x8
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#define UARTCTRL_LOOPS 0x00000080
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#define UARTCTRL_DOZEEN 0x00000040
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#define UARTCTRL_RSRC 0x00000020
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@ -197,6 +198,7 @@
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#define UARTDATA_MASK 0x3ff
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#define UARTMODIR_IREN 0x00020000
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#define UARTMODIR_RTSWATER_S 0x8
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#define UARTMODIR_TXCTSSRC 0x00000020
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#define UARTMODIR_TXCTSC 0x00000010
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#define UARTMODIR_RXRTSE 0x00000008
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@ -210,6 +212,8 @@
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#define UARTFIFO_RXUF 0x00010000
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#define UARTFIFO_TXFLUSH 0x00008000
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#define UARTFIFO_RXFLUSH 0x00004000
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#define UARTFIFO_RXIDEN_MASK 0x7
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#define UARTFIFO_RXIDEN_OFF 10
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#define UARTFIFO_TXOFE 0x00000200
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#define UARTFIFO_RXUFE 0x00000100
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#define UARTFIFO_TXFE 0x00000080
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@ -226,6 +230,9 @@
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#define UARTWATER_TXWATER_OFF 0
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#define UARTWATER_RXWATER_OFF 16
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#define UARTFIFO_RXIDEN_RDRF 0x3
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#define UARTCTRL_IDLECFG 0x7
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/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
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#define DMA_RX_TIMEOUT (10)
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@ -253,6 +260,9 @@ struct lpuart_port {
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unsigned int txfifo_size;
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unsigned int rxfifo_size;
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u8 rx_watermark;
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bool dma_eeop;
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bool rx_dma_cyclic;
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bool lpuart_dma_tx_use;
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bool lpuart_dma_rx_use;
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struct dma_chan *dma_tx_chan;
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@ -277,28 +287,38 @@ struct lpuart_soc_data {
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enum lpuart_type devtype;
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char iotype;
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u8 reg_off;
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u8 rx_watermark;
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bool rx_dma_cyclic;
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};
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static const struct lpuart_soc_data vf_data = {
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.devtype = VF610_LPUART,
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.iotype = UPIO_MEM,
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.rx_watermark = 1,
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.rx_dma_cyclic = true,
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};
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static const struct lpuart_soc_data ls_data = {
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.devtype = LS1021A_LPUART,
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.iotype = UPIO_MEM32BE,
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.rx_watermark = 0,
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.rx_dma_cyclic = true,
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};
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static struct lpuart_soc_data imx7ulp_data = {
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.devtype = IMX7ULP_LPUART,
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.iotype = UPIO_MEM32,
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.reg_off = IMX_REG_OFF,
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.rx_watermark = 0,
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.rx_dma_cyclic = true,
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};
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static struct lpuart_soc_data imx8qxp_data = {
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.devtype = IMX8QXP_LPUART,
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.iotype = UPIO_MEM32,
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.reg_off = IMX_REG_OFF,
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.rx_watermark = 31,
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.rx_dma_cyclic = false,
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};
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static const struct of_device_id lpuart_dt_ids[] = {
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@ -312,6 +332,7 @@ MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
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/* Forward declare this for the dma callbacks*/
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static void lpuart_dma_tx_complete(void *arg);
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static int lpuart_sched_rx_dma(struct lpuart_port *sport);
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static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
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{
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@ -999,19 +1020,15 @@ static irqreturn_t lpuart32_int(int irq, void *dev_id)
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if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
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lpuart32_txint(sport);
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if (sport->lpuart_dma_rx_use && sport->dma_eeop)
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sts &= ~UARTSTAT_IDLE;
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lpuart32_write(&sport->port, sts, UARTSTAT);
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return IRQ_HANDLED;
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}
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static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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static void lpuart_rx_error_stat(struct lpuart_port *sport)
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{
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struct tty_port *port = &sport->port.state->port;
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struct dma_tx_state state;
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enum dma_status dmastat;
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struct circ_buf *ring = &sport->rx_ring;
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unsigned long flags;
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int count = 0;
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if (lpuart_is_32(sport)) {
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unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
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@ -1063,8 +1080,21 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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writeb(cr2, sport->port.membase + UARTCR2);
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}
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}
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}
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async_tx_ack(sport->dma_rx_desc);
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static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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{
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struct tty_port *port = &sport->port.state->port;
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struct dma_tx_state state;
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enum dma_status dmastat;
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struct circ_buf *ring = &sport->rx_ring;
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unsigned long flags;
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int count = 0;
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if (!is_imx8qxp_lpuart(sport)) {
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lpuart_rx_error_stat(sport);
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async_tx_ack(sport->dma_rx_desc);
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}
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spin_lock_irqsave(&sport->port.lock, flags);
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@ -1127,7 +1157,33 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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spin_unlock_irqrestore(&sport->port.lock, flags);
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tty_flip_buffer_push(port);
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mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
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if (!sport->dma_eeop)
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mod_timer(&sport->lpuart_timer,
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jiffies + sport->dma_rx_timeout);
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}
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static void lpuart_dma_rx_post_handler(struct lpuart_port *sport)
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{
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unsigned long flags;
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unsigned long rxcount;
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spin_lock_irqsave(&sport->port.lock, flags);
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/* For end of packet, clear the idle flag to avoid to trigger
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* the next transfer. Only i.MX8x lpuart support EEOP.
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*/
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if (sport->dma_eeop && lpuart_is_32(sport)) {
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rxcount = lpuart32_read(&sport->port, UARTWATER);
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rxcount = rxcount >> UARTWATER_RXCNT_OFF;
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if (!rxcount)
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lpuart32_write(&sport->port, UARTSTAT_IDLE, UARTSTAT);
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}
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lpuart_sched_rx_dma(sport);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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}
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static void lpuart_dma_rx_complete(void *arg)
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@ -1135,6 +1191,8 @@ static void lpuart_dma_rx_complete(void *arg)
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struct lpuart_port *sport = arg;
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lpuart_copy_rx_to_tty(sport);
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if (!sport->rx_dma_cyclic)
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lpuart_dma_rx_post_handler(sport);
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}
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static void lpuart_timer_func(struct timer_list *t)
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@ -1142,13 +1200,78 @@ static void lpuart_timer_func(struct timer_list *t)
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struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
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lpuart_copy_rx_to_tty(sport);
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if (!sport->rx_dma_cyclic) {
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dmaengine_terminate_async(sport->dma_rx_chan);
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lpuart_dma_rx_post_handler(sport);
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}
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}
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static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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static int lpuart_sched_rxdma_cyclic(struct lpuart_port *sport)
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{
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sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
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sg_dma_address(&sport->rx_sgl),
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sport->rx_sgl.length,
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sport->rx_sgl.length / 2,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!sport->dma_rx_desc) {
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dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
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return -EFAULT;
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}
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return 0;
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}
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static int lpuart_sched_rxdma_slave_sg(struct lpuart_port *sport)
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{
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dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
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DMA_FROM_DEVICE);
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sport->dma_rx_desc = dmaengine_prep_slave_sg(sport->dma_rx_chan,
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&sport->rx_sgl,
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1,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!sport->dma_rx_desc) {
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dev_err(sport->port.dev, "Cannot prepare slave_sg DMA\n");
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return -EFAULT;
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}
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sport->rx_ring.tail = 0;
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sport->rx_ring.head = 0;
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return 0;
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}
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static int lpuart_sched_rx_dma(struct lpuart_port *sport)
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{
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unsigned long temp;
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int ret;
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if (sport->rx_dma_cyclic)
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ret = lpuart_sched_rxdma_cyclic(sport);
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else
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ret = lpuart_sched_rxdma_slave_sg(sport);
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sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
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sport->dma_rx_desc->callback_param = sport;
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sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
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dma_async_issue_pending(sport->dma_rx_chan);
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if (lpuart_is_32(sport)) {
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temp = lpuart32_read(&sport->port, UARTBAUD);
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if (sport->dma_eeop)
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temp |= UARTBAUD_RIDMAE;
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temp |= UARTBAUD_RDMAE;
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lpuart32_write(&sport->port, temp, UARTBAUD);
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} else {
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writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
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sport->port.membase + UARTCR5);
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}
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return ret;
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}
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static void lpuart_get_rx_dma_rng_len(struct lpuart_port *sport)
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{
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struct dma_slave_config dma_rx_sconfig = {};
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struct circ_buf *ring = &sport->rx_ring;
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int ret, nent;
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int bits, baud;
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struct tty_port *port = &sport->port.state->port;
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struct tty_struct *tty = port->tty;
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@ -1168,6 +1291,18 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
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if (sport->rx_dma_rng_buf_len < 16)
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sport->rx_dma_rng_buf_len = 16;
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}
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static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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{
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struct dma_slave_config dma_rx_sconfig = {};
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struct circ_buf *ring = &sport->rx_ring;
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int ret, nent;
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if (!sport->dma_eeop)
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lpuart_get_rx_dma_rng_len(sport);
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else
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sport->rx_dma_rng_buf_len = PAGE_SIZE;
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ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
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if (!ring->buf)
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@ -1193,32 +1328,7 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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return ret;
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}
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sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
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sg_dma_address(&sport->rx_sgl),
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sport->rx_sgl.length,
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sport->rx_sgl.length / 2,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!sport->dma_rx_desc) {
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dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
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return -EFAULT;
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}
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sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
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sport->dma_rx_desc->callback_param = sport;
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sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
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dma_async_issue_pending(sport->dma_rx_chan);
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if (lpuart_is_32(sport)) {
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unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
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lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
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} else {
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writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
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sport->port.membase + UARTCR5);
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}
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return 0;
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return lpuart_sched_rx_dma(sport);
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}
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static void lpuart_dma_rx_free(struct uart_port *port)
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@ -1404,8 +1514,10 @@ static void lpuart_setup_watermark(struct lpuart_port *sport)
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writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
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}
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if (uart_console(&sport->port))
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sport->rx_watermark = 1;
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writeb(0, sport->port.membase + UARTTWFIFO);
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writeb(1, sport->port.membase + UARTRWFIFO);
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writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
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/* Restore cr2 */
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writeb(cr2_saved, sport->port.membase + UARTCR2);
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@ -1426,6 +1538,7 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport)
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{
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unsigned long val, ctrl;
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unsigned long ctrl_saved;
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unsigned long rxiden_cnt;
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ctrl = lpuart32_read(&sport->port, UARTCTRL);
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ctrl_saved = ctrl;
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@ -1437,12 +1550,26 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport)
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val = lpuart32_read(&sport->port, UARTFIFO);
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val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
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val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
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val &= ~(UARTFIFO_RXIDEN_MASK << UARTFIFO_RXIDEN_OFF);
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rxiden_cnt = sport->dma_eeop ? 0 : UARTFIFO_RXIDEN_RDRF;
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val |= ((rxiden_cnt & UARTFIFO_RXIDEN_MASK) <<
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UARTFIFO_RXIDEN_OFF);
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lpuart32_write(&sport->port, val, UARTFIFO);
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/* set the watermark */
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val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
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if (uart_console(&sport->port))
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sport->rx_watermark = 1;
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val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
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(0x0 << UARTWATER_TXWATER_OFF);
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lpuart32_write(&sport->port, val, UARTWATER);
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/* set RTS watermark */
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if (!uart_console(&sport->port)) {
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val = lpuart32_read(&sport->port, UARTMODIR);
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val = (sport->rxfifo_size >> 1) << UARTMODIR_RTSWATER_S;
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lpuart32_write(&sport->port, val, UARTMODIR);
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}
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/* Restore cr2 */
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lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
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}
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@ -1454,17 +1581,29 @@ static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
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lpuart32_setup_watermark(sport);
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temp = lpuart32_read(&sport->port, UARTCTRL);
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temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
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temp |= UARTCTRL_RE | UARTCTRL_TE;
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temp |= UARTCTRL_IDLECFG << UARTCTRL_IDLECFG_OFF;
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lpuart32_write(&sport->port, temp, UARTCTRL);
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}
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static void rx_dma_timer_init(struct lpuart_port *sport)
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{
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if (sport->dma_eeop)
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return;
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timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
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sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
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add_timer(&sport->lpuart_timer);
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}
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static void lpuart_del_timer_sync(struct lpuart_port *sport)
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{
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if (sport->dma_eeop)
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return;
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del_timer_sync(&sport->lpuart_timer);
|
||||
}
|
||||
|
||||
static void lpuart_tx_dma_startup(struct lpuart_port *sport)
|
||||
{
|
||||
u32 uartbaud;
|
||||
|
|
@ -1528,19 +1667,23 @@ static int lpuart_startup(struct uart_port *port)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void lpuart32_hw_disable(struct lpuart_port *sport)
|
||||
{
|
||||
unsigned long temp;
|
||||
|
||||
temp = lpuart32_read(&sport->port, UARTCTRL);
|
||||
temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
|
||||
UARTCTRL_TIE | UARTCTRL_TE);
|
||||
lpuart32_write(&sport->port, temp, UARTCTRL);
|
||||
}
|
||||
|
||||
static void lpuart32_configure(struct lpuart_port *sport)
|
||||
{
|
||||
unsigned long temp;
|
||||
|
||||
if (sport->lpuart_dma_rx_use) {
|
||||
/* RXWATER must be 0 */
|
||||
temp = lpuart32_read(&sport->port, UARTWATER);
|
||||
temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
|
||||
lpuart32_write(&sport->port, temp, UARTWATER);
|
||||
}
|
||||
temp = lpuart32_read(&sport->port, UARTCTRL);
|
||||
if (!sport->lpuart_dma_rx_use)
|
||||
temp |= UARTCTRL_RIE;
|
||||
temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
|
||||
if (!sport->lpuart_dma_tx_use)
|
||||
temp |= UARTCTRL_TIE;
|
||||
lpuart32_write(&sport->port, temp, UARTCTRL);
|
||||
|
|
@ -1573,12 +1716,12 @@ static int lpuart32_startup(struct uart_port *port)
|
|||
|
||||
spin_lock_irqsave(&sport->port.lock, flags);
|
||||
|
||||
lpuart32_setup_watermark_enable(sport);
|
||||
|
||||
lpuart32_hw_disable(sport);
|
||||
|
||||
lpuart_rx_dma_startup(sport);
|
||||
lpuart_tx_dma_startup(sport);
|
||||
|
||||
lpuart32_setup_watermark_enable(sport);
|
||||
lpuart32_configure(sport);
|
||||
|
||||
spin_unlock_irqrestore(&sport->port.lock, flags);
|
||||
|
|
@ -1588,7 +1731,7 @@ static int lpuart32_startup(struct uart_port *port)
|
|||
static void lpuart_dma_shutdown(struct lpuart_port *sport)
|
||||
{
|
||||
if (sport->lpuart_dma_rx_use) {
|
||||
del_timer_sync(&sport->lpuart_timer);
|
||||
lpuart_del_timer_sync(sport);
|
||||
lpuart_dma_rx_free(&sport->port);
|
||||
}
|
||||
|
||||
|
|
@ -1629,11 +1772,22 @@ static void lpuart32_shutdown(struct uart_port *port)
|
|||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* clear statue */
|
||||
temp = lpuart32_read(&sport->port, UARTSTAT);
|
||||
lpuart32_write(&sport->port, temp, UARTSTAT);
|
||||
|
||||
/* disable Rx/Tx DMA */
|
||||
temp = lpuart32_read(port, UARTBAUD);
|
||||
temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE | UARTBAUD_RIDMAE);
|
||||
lpuart32_write(port, temp, UARTBAUD);
|
||||
|
||||
/* disable Rx/Tx and interrupts */
|
||||
temp = lpuart32_read(port, UARTCTRL);
|
||||
temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
|
||||
UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
|
||||
temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_TIE |
|
||||
UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_ILIE |
|
||||
UARTCTRL_LOOPS);
|
||||
lpuart32_write(port, temp, UARTCTRL);
|
||||
lpuart32_write(port, 0, UARTMODIR);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
|
|
@ -1730,10 +1884,10 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
* baud rate and restart Rx DMA path.
|
||||
*
|
||||
* Since timer function acqures sport->port.lock, need to stop before
|
||||
* acquring same lock because otherwise del_timer_sync() can deadlock.
|
||||
* acquring same lock because otherwise lpuart_del_timer_sync() can deadlock.
|
||||
*/
|
||||
if (old && sport->lpuart_dma_rx_use) {
|
||||
del_timer_sync(&sport->lpuart_timer);
|
||||
lpuart_del_timer_sync(sport);
|
||||
lpuart_dma_rx_free(&sport->port);
|
||||
}
|
||||
|
||||
|
|
@ -1945,10 +2099,10 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
* baud rate and restart Rx DMA path.
|
||||
*
|
||||
* Since timer function acqures sport->port.lock, need to stop before
|
||||
* acquring same lock because otherwise del_timer_sync() can deadlock.
|
||||
* acquring same lock because otherwise lpuart_del_timer_sync() can deadlock.
|
||||
*/
|
||||
if (old && sport->lpuart_dma_rx_use) {
|
||||
del_timer_sync(&sport->lpuart_timer);
|
||||
lpuart_del_timer_sync(sport);
|
||||
lpuart_dma_rx_free(&sport->port);
|
||||
}
|
||||
|
||||
|
|
@ -2470,6 +2624,10 @@ static int lpuart_probe(struct platform_device *pdev)
|
|||
sport->port.dev = &pdev->dev;
|
||||
sport->port.type = PORT_LPUART;
|
||||
sport->devtype = sdata->devtype;
|
||||
sport->rx_dma_cyclic = sdata->rx_dma_cyclic;
|
||||
sport->rx_watermark = sdata->rx_watermark;
|
||||
sport->dma_eeop = is_imx8qxp_lpuart(sport);
|
||||
|
||||
ret = platform_get_irq(pdev, 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
|
@ -2611,7 +2769,7 @@ static int lpuart_suspend(struct device *dev)
|
|||
* Rx DMA path before suspend and start Rx DMA path on resume.
|
||||
*/
|
||||
if (irq_wake) {
|
||||
del_timer_sync(&sport->lpuart_timer);
|
||||
lpuart_del_timer_sync(sport);
|
||||
lpuart_dma_rx_free(&sport->port);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue