net/mlx5: Update transobj.c new cmd interface
Do mass update of transobj.c to reuse newly introduced mlx5_cmd_exec_in*() interfaces. Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
This commit is contained in:
Leon Romanovsky
parent
7ba294e435
commit
e0b4b4722d
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@ -1255,7 +1255,7 @@ static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
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struct mlx5_ib_sq *sq, u32 tdn,
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struct ib_pd *pd)
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{
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u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
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u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
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void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
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MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
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@ -1263,7 +1263,7 @@ static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
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if (qp->flags & MLX5_IB_QP_UNDERLAY)
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MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
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return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
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return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
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}
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static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
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@ -1460,9 +1460,8 @@ static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
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static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
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struct mlx5_ib_rq *rq, u32 tdn,
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u32 *qp_flags_en,
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struct ib_pd *pd,
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u32 *out, int outlen)
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u32 *qp_flags_en, struct ib_pd *pd,
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u32 *out)
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{
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u8 lb_flag = 0;
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u32 *in;
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@ -1495,9 +1494,8 @@ static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
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}
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MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
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err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen);
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MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
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err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
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rq->tirn = MLX5_GET(create_tir_out, out, tirn);
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if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
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err = mlx5_ib_enable_lb(dev, false, true);
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@ -1557,9 +1555,8 @@ static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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if (err)
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goto err_destroy_sq;
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err = create_raw_packet_qp_tir(
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dev, rq, tdn, &qp->flags_en, pd, out,
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MLX5_ST_SZ_BYTES(create_tir_out));
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err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
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out);
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if (err)
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goto err_destroy_rq;
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@ -1854,7 +1851,8 @@ static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
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create_tir:
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err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen);
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MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
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err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
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qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
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if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
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@ -2933,7 +2931,7 @@ static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
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tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
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MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
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err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
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err = mlx5_core_modify_tis(dev, sq->tisn, in);
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kvfree(in);
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@ -2960,7 +2958,7 @@ static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
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tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
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MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
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err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
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err = mlx5_core_modify_tis(dev, sq->tisn, in);
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kvfree(in);
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@ -3240,7 +3238,7 @@ static int modify_raw_packet_qp_rq(
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"RAW PACKET QP counters are not supported on current FW\n");
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}
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err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
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err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
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if (err)
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goto out;
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@ -3303,7 +3301,7 @@ static int modify_raw_packet_qp_sq(
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MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
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}
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err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
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err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
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if (err) {
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/* Remove new rate from table if failed */
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if (new_rate_added)
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@ -6444,7 +6442,7 @@ int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
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"Receive WQ counters are not supported on current FW\n");
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}
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err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
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err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
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if (!err)
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rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
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@ -1012,7 +1012,7 @@ int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
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void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
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const struct mlx5e_tirc_config *ttconfig,
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void *tirc, bool inner);
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void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
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void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in);
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struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
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struct mlx5e_xsk_param;
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@ -1102,8 +1102,8 @@ void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
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void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
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#endif
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int mlx5e_create_tir(struct mlx5_core_dev *mdev,
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struct mlx5e_tir *tir, u32 *in, int inlen);
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int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir,
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u32 *in);
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void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
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struct mlx5e_tir *tir);
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int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
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@ -36,12 +36,11 @@
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* Global resources are common to all the netdevices crated on the same nic.
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*/
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int mlx5e_create_tir(struct mlx5_core_dev *mdev,
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struct mlx5e_tir *tir, u32 *in, int inlen)
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int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir, u32 *in)
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{
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int err;
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err = mlx5_core_create_tir(mdev, in, inlen, &tir->tirn);
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err = mlx5_core_create_tir(mdev, in, &tir->tirn);
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if (err)
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return err;
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@ -167,7 +166,7 @@ int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb)
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mutex_lock(&mdev->mlx5e_res.td.list_lock);
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list_for_each_entry(tir, &mdev->mlx5e_res.td.tirs_list, list) {
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tirn = tir->tirn;
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err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
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err = mlx5_core_modify_tir(mdev, tirn, in);
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if (err)
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goto out;
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}
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@ -1204,7 +1204,7 @@ int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
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}
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if (hash_changed)
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mlx5e_modify_tirs_hash(priv, in, inlen);
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mlx5e_modify_tirs_hash(priv, in);
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mutex_unlock(&priv->state_lock);
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@ -858,7 +858,7 @@ static int mlx5e_set_rss_hash_opt(struct mlx5e_priv *priv,
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goto out;
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priv->rss_params.rx_hash_fields[tt] = rx_hash_field;
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mlx5e_modify_tirs_hash(priv, in, inlen);
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mlx5e_modify_tirs_hash(priv, in);
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out:
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mutex_unlock(&priv->state_lock);
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@ -721,7 +721,7 @@ int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
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MLX5_SET(modify_rq_in, in, rq_state, curr_state);
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MLX5_SET(rqc, rqc, state, next_state);
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err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
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err = mlx5_core_modify_rq(mdev, rq->rqn, in);
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kvfree(in);
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@ -752,7 +752,7 @@ static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
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MLX5_SET(rqc, rqc, scatter_fcs, enable);
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MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
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err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
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err = mlx5_core_modify_rq(mdev, rq->rqn, in);
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kvfree(in);
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@ -781,7 +781,7 @@ static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
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MLX5_SET(rqc, rqc, vsd, vsd);
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MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
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err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
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err = mlx5_core_modify_rq(mdev, rq->rqn, in);
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kvfree(in);
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@ -1259,7 +1259,7 @@ int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
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MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
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}
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err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
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err = mlx5_core_modify_sq(mdev, sqn, in);
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kvfree(in);
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@ -2698,7 +2698,7 @@ static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
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ttconfig->rx_hash_fields = rx_hash_fields;
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}
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void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
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void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
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{
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void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
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struct mlx5e_rss_params *rss = &priv->rss_params;
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@ -2714,7 +2714,7 @@ void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
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mlx5e_update_rx_hash_fields(&ttconfig, tt,
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rss->rx_hash_fields[tt]);
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mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
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mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
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mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
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}
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if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
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@ -2725,8 +2725,7 @@ void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
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mlx5e_update_rx_hash_fields(&ttconfig, tt,
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rss->rx_hash_fields[tt]);
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mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
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mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
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inlen);
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mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
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}
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}
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@ -2752,15 +2751,13 @@ static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
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mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
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for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
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err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
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inlen);
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err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
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if (err)
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goto free_in;
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}
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for (ix = 0; ix < priv->max_nch; ix++) {
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err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
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in, inlen);
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err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
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if (err)
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goto free_in;
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}
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@ -3214,7 +3211,7 @@ int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
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if (mlx5_lag_is_lacp_owner(mdev))
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MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
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return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
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return mlx5_core_create_tis(mdev, in, tisn);
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}
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void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
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@ -3332,7 +3329,7 @@ int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
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tir = &priv->indir_tir[tt];
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tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
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mlx5e_build_indir_tir_ctx(priv, tt, tirc);
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err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
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err = mlx5e_create_tir(priv->mdev, tir, in);
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if (err) {
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mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
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goto err_destroy_inner_tirs;
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@ -3347,7 +3344,7 @@ int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
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tir = &priv->inner_indir_tir[i];
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tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
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mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
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err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
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err = mlx5e_create_tir(priv->mdev, tir, in);
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if (err) {
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mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
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goto err_destroy_inner_tirs;
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@ -3390,7 +3387,7 @@ int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
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tir = &tirs[ix];
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tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
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mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
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err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
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err = mlx5e_create_tir(priv->mdev, tir, in);
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if (unlikely(err))
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goto err_destroy_ch_tirs;
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}
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@ -568,7 +568,7 @@ struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
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static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
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{
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u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
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u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
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void *tirc;
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int err;
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@ -582,7 +582,7 @@ static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
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MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
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MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
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err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
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err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
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if (err)
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goto create_tir_err;
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@ -666,7 +666,7 @@ static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
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mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
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err = mlx5_core_create_tir(hp->func_mdev, in,
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MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
|
||||
&hp->indir_tirn[tt]);
|
||||
if (err) {
|
||||
mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
|
||||
goto err_destroy_tirs;
|
||||
|
|
|
|||
|
|
@ -36,14 +36,14 @@
|
|||
|
||||
int mlx5_core_alloc_transport_domain(struct mlx5_core_dev *dev, u32 *tdn)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {};
|
||||
u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {};
|
||||
int err;
|
||||
|
||||
MLX5_SET(alloc_transport_domain_in, in, opcode,
|
||||
MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
|
||||
|
||||
err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
||||
err = mlx5_cmd_exec_inout(dev, alloc_transport_domain, in, out);
|
||||
if (!err)
|
||||
*tdn = MLX5_GET(alloc_transport_domain_out, out,
|
||||
transport_domain);
|
||||
|
|
@ -54,19 +54,18 @@ EXPORT_SYMBOL(mlx5_core_alloc_transport_domain);
|
|||
|
||||
void mlx5_core_dealloc_transport_domain(struct mlx5_core_dev *dev, u32 tdn)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(dealloc_transport_domain_out)] = {0};
|
||||
u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {};
|
||||
|
||||
MLX5_SET(dealloc_transport_domain_in, in, opcode,
|
||||
MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN);
|
||||
MLX5_SET(dealloc_transport_domain_in, in, transport_domain, tdn);
|
||||
mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
||||
mlx5_cmd_exec_in(dev, dealloc_transport_domain, in);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_dealloc_transport_domain);
|
||||
|
||||
int mlx5_core_create_rq(struct mlx5_core_dev *dev, u32 *in, int inlen, u32 *rqn)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {};
|
||||
int err;
|
||||
|
||||
MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
|
||||
|
|
@ -78,44 +77,39 @@ int mlx5_core_create_rq(struct mlx5_core_dev *dev, u32 *in, int inlen, u32 *rqn)
|
|||
}
|
||||
EXPORT_SYMBOL(mlx5_core_create_rq);
|
||||
|
||||
int mlx5_core_modify_rq(struct mlx5_core_dev *dev, u32 rqn, u32 *in, int inlen)
|
||||
int mlx5_core_modify_rq(struct mlx5_core_dev *dev, u32 rqn, u32 *in)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(modify_rq_out)];
|
||||
|
||||
MLX5_SET(modify_rq_in, in, rqn, rqn);
|
||||
MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
|
||||
|
||||
memset(out, 0, sizeof(out));
|
||||
return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
|
||||
return mlx5_cmd_exec_in(dev, modify_rq, in);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_modify_rq);
|
||||
|
||||
void mlx5_core_destroy_rq(struct mlx5_core_dev *dev, u32 rqn)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {0};
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {};
|
||||
|
||||
MLX5_SET(destroy_rq_in, in, opcode, MLX5_CMD_OP_DESTROY_RQ);
|
||||
MLX5_SET(destroy_rq_in, in, rqn, rqn);
|
||||
mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
||||
mlx5_cmd_exec_in(dev, destroy_rq, in);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_destroy_rq);
|
||||
|
||||
int mlx5_core_query_rq(struct mlx5_core_dev *dev, u32 rqn, u32 *out)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
|
||||
int outlen = MLX5_ST_SZ_BYTES(query_rq_out);
|
||||
u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {};
|
||||
|
||||
MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
|
||||
MLX5_SET(query_rq_in, in, rqn, rqn);
|
||||
|
||||
return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
|
||||
return mlx5_cmd_exec_inout(dev, query_rq, in, out);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_query_rq);
|
||||
|
||||
int mlx5_core_create_sq(struct mlx5_core_dev *dev, u32 *in, int inlen, u32 *sqn)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {};
|
||||
int err;
|
||||
|
||||
MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
|
||||
|
|
@ -126,34 +120,30 @@ int mlx5_core_create_sq(struct mlx5_core_dev *dev, u32 *in, int inlen, u32 *sqn)
|
|||
return err;
|
||||
}
|
||||
|
||||
int mlx5_core_modify_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *in, int inlen)
|
||||
int mlx5_core_modify_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *in)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
|
||||
|
||||
MLX5_SET(modify_sq_in, in, sqn, sqn);
|
||||
MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
|
||||
return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
|
||||
return mlx5_cmd_exec_in(dev, modify_sq, in);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_modify_sq);
|
||||
|
||||
void mlx5_core_destroy_sq(struct mlx5_core_dev *dev, u32 sqn)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(destroy_sq_out)] = {0};
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {};
|
||||
|
||||
MLX5_SET(destroy_sq_in, in, opcode, MLX5_CMD_OP_DESTROY_SQ);
|
||||
MLX5_SET(destroy_sq_in, in, sqn, sqn);
|
||||
mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
||||
mlx5_cmd_exec_in(dev, destroy_sq, in);
|
||||
}
|
||||
|
||||
int mlx5_core_query_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *out)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(query_sq_in)] = {0};
|
||||
int outlen = MLX5_ST_SZ_BYTES(query_sq_out);
|
||||
u32 in[MLX5_ST_SZ_DW(query_sq_in)] = {};
|
||||
|
||||
MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ);
|
||||
MLX5_SET(query_sq_in, in, sqn, sqn);
|
||||
return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
|
||||
return mlx5_cmd_exec_inout(dev, query_sq, in, out);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_query_sq);
|
||||
|
||||
|
|
@ -182,24 +172,13 @@ out:
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(mlx5_core_query_sq_state);
|
||||
|
||||
int mlx5_core_create_tir_out(struct mlx5_core_dev *dev,
|
||||
u32 *in, int inlen,
|
||||
u32 *out, int outlen)
|
||||
{
|
||||
MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
|
||||
|
||||
return mlx5_cmd_exec(dev, in, inlen, out, outlen);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_create_tir_out);
|
||||
|
||||
int mlx5_core_create_tir(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
||||
u32 *tirn)
|
||||
int mlx5_core_create_tir(struct mlx5_core_dev *dev, u32 *in, u32 *tirn)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
|
||||
int err;
|
||||
|
||||
err = mlx5_core_create_tir_out(dev, in, inlen,
|
||||
out, sizeof(out));
|
||||
MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
|
||||
err = mlx5_cmd_exec_inout(dev, create_tir, in, out);
|
||||
if (!err)
|
||||
*tirn = MLX5_GET(create_tir_out, out, tirn);
|
||||
|
||||
|
|
@ -207,35 +186,30 @@ int mlx5_core_create_tir(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
|||
}
|
||||
EXPORT_SYMBOL(mlx5_core_create_tir);
|
||||
|
||||
int mlx5_core_modify_tir(struct mlx5_core_dev *dev, u32 tirn, u32 *in,
|
||||
int inlen)
|
||||
int mlx5_core_modify_tir(struct mlx5_core_dev *dev, u32 tirn, u32 *in)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
|
||||
|
||||
MLX5_SET(modify_tir_in, in, tirn, tirn);
|
||||
MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
|
||||
return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
|
||||
return mlx5_cmd_exec_in(dev, modify_tir, in);
|
||||
}
|
||||
|
||||
void mlx5_core_destroy_tir(struct mlx5_core_dev *dev, u32 tirn)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(destroy_tir_out)] = {0};
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {};
|
||||
|
||||
MLX5_SET(destroy_tir_in, in, opcode, MLX5_CMD_OP_DESTROY_TIR);
|
||||
MLX5_SET(destroy_tir_in, in, tirn, tirn);
|
||||
mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
||||
mlx5_cmd_exec_in(dev, destroy_tir, in);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_destroy_tir);
|
||||
|
||||
int mlx5_core_create_tis(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
||||
u32 *tisn)
|
||||
int mlx5_core_create_tis(struct mlx5_core_dev *dev, u32 *in, u32 *tisn)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(create_tis_out)] = {};
|
||||
int err;
|
||||
|
||||
MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
|
||||
err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
|
||||
err = mlx5_cmd_exec_inout(dev, create_tis, in, out);
|
||||
if (!err)
|
||||
*tisn = MLX5_GET(create_tis_out, out, tisn);
|
||||
|
||||
|
|
@ -243,33 +217,29 @@ int mlx5_core_create_tis(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
|||
}
|
||||
EXPORT_SYMBOL(mlx5_core_create_tis);
|
||||
|
||||
int mlx5_core_modify_tis(struct mlx5_core_dev *dev, u32 tisn, u32 *in,
|
||||
int inlen)
|
||||
int mlx5_core_modify_tis(struct mlx5_core_dev *dev, u32 tisn, u32 *in)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(modify_tis_out)] = {0};
|
||||
|
||||
MLX5_SET(modify_tis_in, in, tisn, tisn);
|
||||
MLX5_SET(modify_tis_in, in, opcode, MLX5_CMD_OP_MODIFY_TIS);
|
||||
|
||||
return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
|
||||
return mlx5_cmd_exec_in(dev, modify_tis, in);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_modify_tis);
|
||||
|
||||
void mlx5_core_destroy_tis(struct mlx5_core_dev *dev, u32 tisn)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(destroy_tis_out)] = {0};
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {};
|
||||
|
||||
MLX5_SET(destroy_tis_in, in, opcode, MLX5_CMD_OP_DESTROY_TIS);
|
||||
MLX5_SET(destroy_tis_in, in, tisn, tisn);
|
||||
mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
||||
mlx5_cmd_exec_in(dev, destroy_tis, in);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_destroy_tis);
|
||||
|
||||
int mlx5_core_create_rqt(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
||||
u32 *rqtn)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {};
|
||||
int err;
|
||||
|
||||
MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
|
||||
|
|
@ -284,7 +254,7 @@ EXPORT_SYMBOL(mlx5_core_create_rqt);
|
|||
int mlx5_core_modify_rqt(struct mlx5_core_dev *dev, u32 rqtn, u32 *in,
|
||||
int inlen)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(modify_rqt_out)] = {};
|
||||
|
||||
MLX5_SET(modify_rqt_in, in, rqtn, rqtn);
|
||||
MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
|
||||
|
|
@ -293,12 +263,11 @@ int mlx5_core_modify_rqt(struct mlx5_core_dev *dev, u32 rqtn, u32 *in,
|
|||
|
||||
void mlx5_core_destroy_rqt(struct mlx5_core_dev *dev, u32 rqtn)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {};
|
||||
|
||||
MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
|
||||
MLX5_SET(destroy_rqt_in, in, rqtn, rqtn);
|
||||
mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
||||
mlx5_cmd_exec_in(dev, destroy_rqt, in);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_core_destroy_rqt);
|
||||
|
||||
|
|
@ -383,7 +352,7 @@ static int mlx5_hairpin_modify_rq(struct mlx5_core_dev *func_mdev, u32 rqn,
|
|||
int curr_state, int next_state,
|
||||
u16 peer_vhca, u32 peer_sq)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
|
||||
u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {};
|
||||
void *rqc;
|
||||
|
||||
rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
|
||||
|
|
@ -396,8 +365,7 @@ static int mlx5_hairpin_modify_rq(struct mlx5_core_dev *func_mdev, u32 rqn,
|
|||
MLX5_SET(modify_rq_in, in, rq_state, curr_state);
|
||||
MLX5_SET(rqc, rqc, state, next_state);
|
||||
|
||||
return mlx5_core_modify_rq(func_mdev, rqn,
|
||||
in, MLX5_ST_SZ_BYTES(modify_rq_in));
|
||||
return mlx5_core_modify_rq(func_mdev, rqn, in);
|
||||
}
|
||||
|
||||
static int mlx5_hairpin_modify_sq(struct mlx5_core_dev *peer_mdev, u32 sqn,
|
||||
|
|
@ -417,8 +385,7 @@ static int mlx5_hairpin_modify_sq(struct mlx5_core_dev *peer_mdev, u32 sqn,
|
|||
MLX5_SET(modify_sq_in, in, sq_state, curr_state);
|
||||
MLX5_SET(sqc, sqc, state, next_state);
|
||||
|
||||
return mlx5_core_modify_sq(peer_mdev, sqn,
|
||||
in, MLX5_ST_SZ_BYTES(modify_sq_in));
|
||||
return mlx5_core_modify_sq(peer_mdev, sqn, in);
|
||||
}
|
||||
|
||||
static int mlx5_hairpin_pair_queues(struct mlx5_hairpin *hp)
|
||||
|
|
|
|||
|
|
@ -39,27 +39,20 @@ int mlx5_core_alloc_transport_domain(struct mlx5_core_dev *dev, u32 *tdn);
|
|||
void mlx5_core_dealloc_transport_domain(struct mlx5_core_dev *dev, u32 tdn);
|
||||
int mlx5_core_create_rq(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
||||
u32 *rqn);
|
||||
int mlx5_core_modify_rq(struct mlx5_core_dev *dev, u32 rqn, u32 *in, int inlen);
|
||||
int mlx5_core_modify_rq(struct mlx5_core_dev *dev, u32 rqn, u32 *in);
|
||||
void mlx5_core_destroy_rq(struct mlx5_core_dev *dev, u32 rqn);
|
||||
int mlx5_core_query_rq(struct mlx5_core_dev *dev, u32 rqn, u32 *out);
|
||||
int mlx5_core_create_sq(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
||||
u32 *sqn);
|
||||
int mlx5_core_modify_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *in, int inlen);
|
||||
int mlx5_core_modify_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *in);
|
||||
void mlx5_core_destroy_sq(struct mlx5_core_dev *dev, u32 sqn);
|
||||
int mlx5_core_query_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *out);
|
||||
int mlx5_core_query_sq_state(struct mlx5_core_dev *dev, u32 sqn, u8 *state);
|
||||
int mlx5_core_create_tir(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
||||
u32 *tirn);
|
||||
int mlx5_core_create_tir_out(struct mlx5_core_dev *dev,
|
||||
u32 *in, int inlen,
|
||||
u32 *out, int outlen);
|
||||
int mlx5_core_modify_tir(struct mlx5_core_dev *dev, u32 tirn, u32 *in,
|
||||
int inlen);
|
||||
int mlx5_core_create_tir(struct mlx5_core_dev *dev, u32 *in, u32 *tirn);
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int mlx5_core_modify_tir(struct mlx5_core_dev *dev, u32 tirn, u32 *in);
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void mlx5_core_destroy_tir(struct mlx5_core_dev *dev, u32 tirn);
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||||
int mlx5_core_create_tis(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
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u32 *tisn);
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int mlx5_core_modify_tis(struct mlx5_core_dev *dev, u32 tisn, u32 *in,
|
||||
int inlen);
|
||||
int mlx5_core_create_tis(struct mlx5_core_dev *dev, u32 *in, u32 *tisn);
|
||||
int mlx5_core_modify_tis(struct mlx5_core_dev *dev, u32 tisn, u32 *in);
|
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void mlx5_core_destroy_tis(struct mlx5_core_dev *dev, u32 tisn);
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||||
int mlx5_core_create_rqt(struct mlx5_core_dev *dev, u32 *in, int inlen,
|
||||
u32 *rqtn);
|
||||
|
|
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Loading…
Reference in a new issue