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drm/amdgpu: update golden setting programming logic 

Since from soc15, make sure only AndMasked bit get changed
when applied or_mask

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
alistair/sunxi64-5.4-dsi
Hawking Zhang 2018-06-08 18:10:57 +08:00 committed by Alex Deucher
parent 6bdadb2072
commit e0d076574e
2 changed files with 5 additions and 2 deletions
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5
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -509,7 +509,10 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
} else {
tmp = RREG32(reg);
tmp &= ~and_mask;
tmp |= or_mask;
if (adev->family >= AMDGPU_FAMILY_AI)
tmp |= (or_mask & and_mask);
else
tmp |= or_mask;
}
WREG32(reg, tmp);
}

2
drivers/gpu/drm/amd/amdgpu/soc15.c
View File

@ -378,7 +378,7 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
} else {
tmp = RREG32(reg);
tmp &= ~(entry->and_mask);
tmp |= entry->or_mask;
tmp |= (entry->or_mask & entry->and_mask);
}
if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||