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pwm: tegra: Allow 100 % duty cycle 

To get 100 % duty cycle (always high), pulse width needs to be set to
256.

Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
hifive-unleashed-5.1
Victor(Weiguo) Pan 2016-06-22 17:17:20 +05:30 committed by Thierry Reding
parent 5dfbd2bd54
commit e0ee1a75f4
1 changed files with 1 additions and 1 deletions
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2
drivers/pwm/pwm-tegra.c
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@ -77,7 +77,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
* nearest integer during division.
*/
c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;
do_div(c, period_ns);
val = (u32)c << PWM_DUTY_SHIFT;