net: switch to using PHY_INTERFACE_MODE_10GBASER rather than 10GKR
Switch network drivers, phy drivers, and SFP/phylink over to use the more correct 10GBASE-R, rather than 10GBASE-KR. 10GBASE-KR is backplane ethernet, which is 10GBASE-R with autonegotiation on top, which our current usage on the affected platforms does not have. The only remaining user of PHY_INTERFACE_MODE_10GKR is the Aquantia PHY, which has a separate mode for 10GBASE-KR. For Marvell mvpp2, we detect 10GBASE-KR, and rewrite it to 10GBASE-R for compatibility with existing DT - this is the only network driver at present that makes use of PHY_INTERFACE_MODE_10GKR. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>alistair/sensors
parent
c114574ebf
commit
e0f909bc3a
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@ -1114,7 +1114,7 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
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/* Port configuration routines */
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static bool mvpp2_is_xlg(phy_interface_t interface)
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{
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return interface == PHY_INTERFACE_MODE_10GKR ||
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return interface == PHY_INTERFACE_MODE_10GBASER ||
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interface == PHY_INTERFACE_MODE_XAUI;
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}
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@ -1200,7 +1200,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
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case PHY_INTERFACE_MODE_2500BASEX:
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mvpp22_gop_init_sgmii(port);
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break;
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case PHY_INTERFACE_MODE_10GKR:
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case PHY_INTERFACE_MODE_10GBASER:
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if (port->gop_id != 0)
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goto invalid_conf;
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mvpp22_gop_init_10gkr(port);
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@ -1649,7 +1649,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
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xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
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switch (port->phy_interface) {
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case PHY_INTERFACE_MODE_10GKR:
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case PHY_INTERFACE_MODE_10GBASER:
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val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
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val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
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MAC_CLK_RESET_SD_TX;
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@ -4758,7 +4758,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
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/* Invalid combinations */
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switch (state->interface) {
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case PHY_INTERFACE_MODE_10GKR:
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_XAUI:
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if (port->gop_id != 0)
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goto empty_set;
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@ -4780,7 +4780,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
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phylink_set(mask, Asym_Pause);
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switch (state->interface) {
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case PHY_INTERFACE_MODE_10GKR:
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_XAUI:
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case PHY_INTERFACE_MODE_NA:
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if (port->gop_id == 0) {
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@ -5247,6 +5247,15 @@ static int mvpp2_port_probe(struct platform_device *pdev,
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goto err_free_netdev;
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}
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/*
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* Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
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* Existing usage of 10GBASE-KR is not correct; no backplane
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* negotiation is done, and this driver does not actually support
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* 10GBASE-KR.
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*/
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if (phy_mode == PHY_INTERFACE_MODE_10GKR)
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phy_mode = PHY_INTERFACE_MODE_10GBASER;
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if (port_node) {
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comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
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if (IS_ERR(comphy)) {
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@ -358,9 +358,11 @@ static int aqr107_read_status(struct phy_device *phydev)
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switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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break;
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
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phydev->interface = PHY_INTERFACE_MODE_10GBASER;
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break;
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
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phydev->interface = PHY_INTERFACE_MODE_USXGMII;
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break;
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@ -493,7 +495,8 @@ static int aqr107_config_init(struct phy_device *phydev)
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phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
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phydev->interface != PHY_INTERFACE_MODE_XGMII &&
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phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
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phydev->interface != PHY_INTERFACE_MODE_10GKR)
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phydev->interface != PHY_INTERFACE_MODE_10GKR &&
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phydev->interface != PHY_INTERFACE_MODE_10GBASER)
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return -ENODEV;
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WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
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@ -53,7 +53,7 @@ static int bcm84881_config_init(struct phy_device *phydev)
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_2500BASEX:
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case PHY_INTERFACE_MODE_10GKR:
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case PHY_INTERFACE_MODE_10GBASER:
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break;
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default:
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return -ENODEV;
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@ -218,7 +218,7 @@ static int bcm84881_read_status(struct phy_device *phydev)
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if (mode == 1 || mode == 2)
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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else if (mode == 3)
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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phydev->interface = PHY_INTERFACE_MODE_10GBASER;
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else if (mode == 4)
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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switch (mode & 7) {
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@ -216,7 +216,7 @@ static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
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sfp_parse_support(phydev->sfp_bus, id, support);
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iface = sfp_select_interface(phydev->sfp_bus, support);
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if (iface != PHY_INTERFACE_MODE_10GKR) {
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if (iface != PHY_INTERFACE_MODE_10GBASER) {
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dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
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return -EINVAL;
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}
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@ -304,7 +304,7 @@ static int mv3310_config_init(struct phy_device *phydev)
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phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
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phydev->interface != PHY_INTERFACE_MODE_XAUI &&
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phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
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phydev->interface != PHY_INTERFACE_MODE_10GKR)
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phydev->interface != PHY_INTERFACE_MODE_10GBASER)
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return -ENODEV;
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return 0;
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@ -386,16 +386,17 @@ static void mv3310_update_interface(struct phy_device *phydev)
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{
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if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
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phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
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phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
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phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
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phydev->link) {
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/* The PHY automatically switches its serdes interface (and
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* active PHYXS instance) between Cisco SGMII, 10GBase-KR and
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* active PHYXS instance) between Cisco SGMII, 10GBase-R and
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* 2500BaseX modes according to the speed. Florian suggests
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* setting phydev->interface to communicate this to the MAC.
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* Only do this if we are already in one of the above modes.
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*/
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switch (phydev->speed) {
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case SPEED_10000:
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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phydev->interface = PHY_INTERFACE_MODE_10GBASER;
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break;
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case SPEED_2500:
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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@ -298,6 +298,7 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
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break;
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case PHY_INTERFACE_MODE_10GKR:
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case PHY_INTERFACE_MODE_10GBASER:
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phylink_set(pl->supported, 10baseT_Half);
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phylink_set(pl->supported, 10baseT_Full);
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phylink_set(pl->supported, 100baseT_Half);
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@ -373,7 +373,7 @@ phy_interface_t sfp_select_interface(struct sfp_bus *bus,
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phylink_test(link_modes, 10000baseLRM_Full) ||
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phylink_test(link_modes, 10000baseER_Full) ||
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phylink_test(link_modes, 10000baseT_Full))
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return PHY_INTERFACE_MODE_10GKR;
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return PHY_INTERFACE_MODE_10GBASER;
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if (phylink_test(link_modes, 2500baseX_Full))
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return PHY_INTERFACE_MODE_2500BASEX;
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@ -221,7 +221,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
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ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
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ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
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ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
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ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
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ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),
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GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
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GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
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GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
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@ -235,14 +235,14 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
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/* lane 4 */
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ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
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ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
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ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
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ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GBASER, 0x2, COMPHY_FW_MODE_XFI),
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ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
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GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
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GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
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GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
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ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
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ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
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ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
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ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),
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/* lane 5 */
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ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
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GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
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@ -342,7 +342,7 @@ static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
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MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE);
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switch (lane->submode) {
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case PHY_INTERFACE_MODE_10GKR:
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case PHY_INTERFACE_MODE_10GBASER:
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val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
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MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
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break;
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@ -417,7 +417,7 @@ static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
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/* refclk selection */
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val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
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val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL;
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if (lane->submode == PHY_INTERFACE_MODE_10GKR)
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if (lane->submode == PHY_INTERFACE_MODE_10GBASER)
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val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE;
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writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
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@ -564,7 +564,7 @@ static int mvebu_comphy_set_mode_rxaui(struct phy *phy)
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return mvebu_comphy_init_plls(lane);
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}
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static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
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static int mvebu_comphy_set_mode_10gbaser(struct phy *phy)
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{
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struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
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struct mvebu_comphy_priv *priv = lane->priv;
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@ -735,8 +735,8 @@ static int mvebu_comphy_power_on_legacy(struct phy *phy)
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case PHY_INTERFACE_MODE_RXAUI:
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ret = mvebu_comphy_set_mode_rxaui(phy);
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break;
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case PHY_INTERFACE_MODE_10GKR:
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ret = mvebu_comphy_set_mode_10gkr(phy);
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case PHY_INTERFACE_MODE_10GBASER:
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ret = mvebu_comphy_set_mode_10gbaser(phy);
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break;
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default:
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return -ENOTSUPP;
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@ -782,8 +782,8 @@ static int mvebu_comphy_power_on(struct phy *phy)
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lane->id);
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fw_speed = COMPHY_FW_SPEED_3125;
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break;
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case PHY_INTERFACE_MODE_10GKR:
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dev_dbg(priv->dev, "set lane %d to 10G-KR mode\n",
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case PHY_INTERFACE_MODE_10GBASER:
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dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",
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lane->id);
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fw_speed = COMPHY_FW_SPEED_103125;
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break;
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